Abstract: A structure is described having a plurality of electronic devices with the same or different internal CMOS voltages; an interconnection between two or more of the electronic devices; driver and receiver circuits which provide selectable input/output voltage levels for interfacing with several generations of CMOS technology, thus allowing chips fabricated in such technologies to communicate using a signal voltage range most suitable for each chip; Circuitry for selecting or adjusting the type of receiver circuit used, thus allowing either the use of a differential comparator circuit with an externally supplied reference voltage, or alternatively, the use of an inverter style receiver with an adjustable threshold, the selection being accomplished by setting the external reference to a predetermined voltage; Circuitry for selecting or adjusting the switching threshold of the inverter receiver circuit, which enables the threshold to be set appropriately for a given input signal voltage range.

Abstract: An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

Abstract: A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.

Abstract: A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.

Abstract: A PGA socket including a plurality of sub-socket components, which when used in combination forms a larger effective socket, includes multiple apertures configured to receive corresponding pins of an IC. The PGA socket further includes multiple contact members, each of the contact members corresponding to a respective one of the apertures. The contact members are configured to movably engage corresponding pins of the IC upon respective movement of the apertures so as to provide electrical and mechanical contact thereto. Each of the sub-socket components is configured to mechanically engage at least one of the other sub-socket components such that the contact members in each of the sub-socket components are capable of electrically connecting to corresponding pins of the IC substantially simultaneously.

Abstract: A three-dimensional architecture chip includes a base chip including a unit integrated thereon and configured to perform electrical signal operations. An active layer is separately fabricated from the base layer. The active layer includes a component to service the unit of the base chip. The active layer is bonded to the base chip such that the component is aligned in vertical proximity of the unit. An electrical connection connects the unit to the component through vertical layers of at least one of the base chip and the active layer.

Abstract: A PGA socket including a plurality of sub-socket components, which when used in combination forms a larger effective socket, includes multiple apertures configured to receive corresponding pins of an IC. The PGA socket further includes multiple contact members, each of the contact members corresponding to a respective one of the apertures. The contact members are configured to movably engage corresponding pins of the IC upon respective movement of the apertures so as to provide electrical and mechanical contact thereto. Each of the sub-socket components is configured to mechanically engage at least one of the other sub-socket components such that the contact members in each of the sub-socket components are capable of electrically connecting to corresponding pins of the IC substantially simultaneously.

Abstract: A PGA socket including a plurality of sub-socket components, which when used in combination forms a larger effective socket, includes multiple apertures configured to receive corresponding pins of an IC. The PGA socket further includes multiple contact members, each of the contact members corresponding to a respective one of the apertures. The contact members are configured to movably engage corresponding pins of the IC upon respective movement of the apertures so as to provide electrical and mechanical contact thereto. Each of the sub-socket components is configured to mechanically engage at least one of the other sub-socket components such that the contact members in each of the sub-socket components are capable of electrically connecting to corresponding pins of the IC substantially simultaneously.

Abstract: A PGA socket including a plurality of sub-socket components, which when used in combination forms a larger effective socket, includes multiple apertures configured to receive corresponding pins of an IC. The PGA socket further includes multiple contact members, each of the contact members corresponding to a respective one of the apertures. The contact members are configured to movably engage corresponding pins of the IC upon respective movement of the apertures so as to provide electrical and mechanical contact thereto. Each of the sub-socket components is configured to mechanically engage at least one of the other sub-socket components such that the contact members in each of the sub-socket components are capable of electrically connecting to corresponding pins of the IC substantially simultaneously.

Abstract: The invention is a selectable function that permits the address portion of data words to be separated from the storable content portion and that address portion to be used for different purposes without disturbing the stored contents in the memory array. The invention may be viewed as a command capability that permits analysis of signals for errors in such items as addresses, impedance calibration, timing, and component drift that develop in and between regions of an overall memory array. Techniques are advanced involving data responsive selectable array circuitry modification for such operations as address correctness verification, machine timing and component drift correction purposes. The principles are illustrated with memory systems built of Synchronous Dynamic Random Access Memory with Double Data Rate (SDRAM-DDR) elements.

Abstract: The providing of an array interface of conductive joint members for use in forming interconnections between mating surfaces such as a pad on a surface mount electronic device and contacts on a circuit card where one portion of the conductive joint members are of a relatively elongated or oval outline and are oriented with the longer dimension in one direction to accommodate wiring spacing and another portion oriented in a different direction for accommodating expansion stress. In manufacturing when the relatively elongated shape is oriented with the longer dimension along the wiping motion direction in a screen type forming of the conductive joint members the slurry of material that is to be the conductive joint members fills the openings in the screen more reliably and the areas of the conductive members are more uniform.

Abstract: A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.

Abstract: The invention teaches a technique for A C equilibration of the signaling levels and time of 1—>h and h—>1 transitions of CMOS drivers as received at CMOS receivers, so as to improve the rate at which data can be communicated between two CMOS devices. It permits minimization of a switching delay in Double Data Rate Dram memories.

Abstract: The invention is a selectable function that permits the address portion of data words to be separated from the storable content portion and that address portion to be used for different purposes without disturbing the stored contents in the memory array. The invention may be viewed as a command capability that permits analysis of signals for errors in such items as addresses, impedance calibration, timing, and component drift that develop in and between regions of an overall memory array.

Abstract: The invention teaches a technique for A C equilibration of the signaling levels and time of 1—>h and h—>1 transitions of CMOS drivers as received at CMOS receivers, so as to improve the rate at which data can be communicated between two CMOS devices.

Abstract: A method and apparatus are disclosed for initiating a start-up operation of a system (1′) having a master device (1) and a slave device (14a-14n). The method comprises steps of: A) exercising the slave device (14a-14n) using the master device (1) to determine a temporal range within which temporal relationships of electrical signals need to be set in order to operate the system (1′) without error; B) setting the temporal relationships of the electrical signals so as to be within the determined temporal range; and C) storing a record of the determined temporal range, for subsequent use in operating the system (1′). In one embodiment of the invention, the system (1′) includes a memory control system of a computer system (1″), and the slave device (14a-14n) includes memory devices of the computer system (1″).

Abstract: A data processing system including an improved method and apparatus for the arrangement and interconnection between electronic devices to improve system cycle time. The apparatus possesses a) a plurality of: memory SIMMs, memory devices on the noted memory SIMMs and registers; b) a clock; c) means for connecting signals between the memory devices on the memory SIMMs and the registers; and d) means for connecting signals between the memory devices on the memory SIMMs and the clocks.

Abstract: The providing of an array interface of conductive joint members for use in forming interconnections between mating surfaces such as a pad on a surface mount electronic device and contacts on a circuit card where one portion of the conductive joint members are of a relatively elongated or oval outline and are oriented with the longer dimension in one direction to accommodate wiring spacing and another portion oriented in a different direction for accommodating expansion stress. In manufacturing when the relatively elongated shape is oriented with the longer dimension along the wiping motion direction in a screen type forming of the conductive joint members the slurry of material that is to be the conductive joint members fills the openings in the screen more reliably and the areas of the conductive members are more uniform.

Abstract: Memory cards for a computer system are placed back-to-back on an active backplane, using wiring topology where the memory address and data busses are wired to pairs of symmetrical connectors. This topology takes advantage of symmetrical memory card pinouts to improve memory bus performance while reducing backplane cost and wiring complexity. The symmetrical layout of the data and address wiring allows two memory cards to be placed back-to-back on the backplane, maintaining the same relative position of data and address pins between cards. Since the data and most of the address lines are common to each card, and any such data or (common or non-unique) address pin on one card can be wired to any other such data or address pin, respectively, on the other card, the back-to-back arrangement provides for minimal address and data bus interconnect lengths between connectors.

Abstract: A first circuit and a second circuit are connected by a pumped signal line that conducts a signal having a plurality of states. A dynamic termination circuit is connected to the pumped signal line. The dynamic termination circuit includes a switch responsive to the signal conducted by the pumped signal line such that the dynamic termination circuit is enabled only in response to certain of the plurality of states of the signal. In one embodiment, the switch is a first transistor that is coupled in series with a first impedance between a first reference voltage and an intermediate node. In this embodiment, the dynamic termination circuit further includes a second transistor coupled in series with a second impedance between a second reference voltage and the intermediate node and only first and second inverters that are each coupled between the intermediate node and the control input of a respective one of the first transistor and the second transistor.