Abstract: A clock signal distribution system is disclosed for providing synchronous clock signals to a plurality of electronic circuit devices. The system includes a clock signal generator means for providing a single frequency sinusoidal clock signal output and a plurality of electronic circuit devices. A clock signal distribution network including interconnected resonant segments of a transmission line 13 connected to the clock signal of the clock signal generator and to the plurality of electronic circuit devices for providing separate synchronous, phase aligned clock signals to the electronic circuit devices. The transmission line segments have lengths matched to the clock signal frequency wavelengths to eliminate clock signal distribution problems such as skew, jitter and pulse distortions.

Abstract: An electronic apparatus is disclosed having: a plurality of electronic devices with the same or different internal voltages; an interconnection between two or more of the plurality of electronic devices; each of said two or more electronic devices has an internal voltage; driver and receiver circuits which send and receive signals at a selectable communication voltage levels for interfacing between said two or more electronic devices, at a common communication voltage which is less than the highest value of said internal voltages of said two or more electronic devices; a circuit for configuring the driver and receiver circuits; and the driver circuit are configured to have a substantially constant output impedance independent of their output voltage.

Abstract: A vital product data (VPD) detection circuit mountable on a substrate of a pluggable component. The circuit comprises a "parallel read" circuit for generating vital product data associated with the pluggable component, a "serial read" circuit for storing and retrieving vital product data associated with the pluggable component, and means for interconnecting the parallel and serial read circuits. The parallel read circuit preferably comprises a parallel array of transistors surface-mounted on the substrate, and the serial read circuit preferably comprises a serial EEPROM having a clock input, a set of address inputs, and a bidirectional data pin. A VPD detection mechanism may disable the parallel VPD circuitry in favor of the serial VPD detection circuitry, or vice versa, or these circuits may be enabled but activated in a mutually exclusive manner.

Abstract: A method and apparatus are provided which are implemented in a chip I/O buffer-multiplexor circuit or I/O buffer cell 201. The I/O buffer portion includes a receiver circuit 205 for receiving bus input signals to the buffered chip, and a driver circuit 203 for driving output signals from the buffered chip to a data bus. An integrated multiplexor or MUX circuit 207 selectively gates one of three possible signals to chip internal logic. The three signals applied to the MUX circuit include a boundary scan test signal BS MUX for testing scan points in an integrated circuit, a bypass Data In signal DI which is generated by chip internal drive logic, and a DQ signal received by the I/O buffer receiver circuit from a data bus. The data input node of the I/O buffer is wired directly to the new multiplexor data input. Additional control signals are provided for orthogonal selection of the three multiplexor data inputs.

Abstract: An arrangement and method for enhancing the cooling capacity of portable personal computers. The power dissipation of portable personal computers (PCs) is increased by conducting heat through a heat pipe arranged in a hinge structure interconnecting a display panel with a bottom keyboard housing, and conducting the heat into an area at the rear of the display panel.

Abstract: This invention describes a new process for the selective isolation of through holes in the production of a multi-layer printed circuit card which allows for substantially smaller holes through reference layers to be built, leading to substantially better electrical isolation of signal traces on adjacent wiring layers, and for substantially improved current carrying capacity in the reference layers. This invention also describes a process to allow reference layers of different thickness from adjacent signal layers, even if they are part of the same `core`. Several different process flows are disclosed, leading to substantially the same structure but with varying degrees of complexity and quality of the finished product.

Abstract: A method and apparatus for detecting the presence/absence of adapter cards such as memory modules and alike. The method and apparatus utilize adapter cards which have wrap around pins for coupling grounds thereto. This coupled ground is then used by a Ground Detection Circuit and combined with different signals emanating from the memory modules such that when one or more of the adapter cards are absent, a default value resulting from the absence of ground is used to indicate the missing adapter(s).

Abstract: An electronic device packaging structure is described which contains a lead frame on which the electronic device is disposed. The electronic device has contact locations at one edge thereof. The lead frame has leads which extend under the electronic device and inwardly from the opposite direction. Wires are wire bonded between electronic device contact locations and the beam leads which extend under the electronic device and the ends of the leads which extend inwardly from the opposite direction. Two electronic devices are stacked in at an offset with respect to each to expose contact locations on the surface of each electronic device at an edge of each electronic device to form a stepped surface exposing a plurality of electronic device contact locations. Preferably, the chips are identical and rotated 180.degree. with respect to each other.

Abstract: The process of the invention employs a post type fastening member that provides, at one end, an insertion friction connection to the circuit card and at the other end, extending through the heat sink, a compression spring means that urges the heat sink toward the cirduit card. A plurality of the post type fasteners are positioned around the periphery of the chip package to retain the heat sink parallel to the circuit card and compressing the chip package. The packaging structure of the invention permits larger area heat sinks than the chip package area to be supported by the circuit card with the only relationship with the chip being that of a compression thermal transfer contact and radiation shield.

Abstract: A system of using a rotatable key in the insertion of a conductor bearing card edge into a slotted supporting connector to accommodate a large number of different cards. A rotatable key opening in the slot face of the slotted supporting connector together with a specific card feature accommodating key positioned in the opening are arranged so that the key can be in one of several positions controlled by the opening with the shape of the key providing an interruption to the continuity of the slot at different distances along the slot length. The card has at least one notch in the insertion edge positioned to be at the slot interruption distance for the particular position of the key. A large number of unique distances are achievable with a single key part.