Patents by Inventor Pavel Konecny

Pavel Konecny has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10739845
    Abstract: An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: August 11, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Praveen Kallam, Johnny Gudmund Bjornsen, Kenneth W. Fernald, Scott Willingham, Pavel Konecny
  • Publication number: 20190163257
    Abstract: An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.
    Type: Application
    Filed: November 26, 2018
    Publication date: May 30, 2019
    Inventors: Praveen Kallam, Johnny Gudmund Bjornsen, Kenneth W. Fernald, Scott Willingham, Pavel Konecny
  • Patent number: 10175271
    Abstract: An apparatus includes an integrated circuit (IC). The IC includes a differencing comparator. The differencing comparator receives a differential input signal. The differencing comparator compares the differential input signal to a threshold value. The differencing comparator includes a transconductance circuit coupled to receive the differential input signal and to provide a differential output signal.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: January 8, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Axel Thomsen, Kenneth W. Fernald, Pavel Konecny
  • Patent number: 10139896
    Abstract: An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: November 27, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Praveen Kallam, Johnny Gudmund Bjornsen, Kenneth W. Fernald, Scott Willingham, Pavel Konecny
  • Patent number: 9590630
    Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: March 7, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Jinwen Xiao, Pavel Konecny, Axel Thomsen, Clayton Daigle, Xiaodong Wang, John Khoury, Alan Westwick, Shahram Tadayon
  • Publication number: 20170010660
    Abstract: An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.
    Type: Application
    Filed: July 8, 2015
    Publication date: January 12, 2017
    Inventors: Praveen Kallam, Johnny Gudmund Bjornsen, Kenneth W. Fernald, Scott Willingham, Pavel Konecny
  • Patent number: 9343971
    Abstract: A capacitor is charged synchronously with the beginning of an ON portion of a pulse width modulated (PWM) signal to generate a voltage across the capacitor using charging current sourced from an inductor on a primary side of a transformer. The voltage is supplied as a supply voltage to control circuitry in an integrated circuit used to generate the pulse width modulated signal. The charging is stopped when either the charging current goes above a predetermined charging current level or when the capacitor voltage goes above a predetermined capacitor voltage.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: May 17, 2016
    Assignee: Silicon Laboratories Inc.
    Inventors: Yeshoda Yedevelly, Pavel Konecny, Wayne T. Holcombe
  • Patent number: 9342084
    Abstract: In one aspect, an apparatus includes a ready circuit to output a ready indicator when a supply voltage provided to the ready circuit and a voltage regulator is sufficient to operate the voltage regulator. In turn, the voltage regulator is to receive the supply voltage and output a regulated voltage, receive a first current from the ready circuit and control the regulated voltage based on the first current when the ready indicator is inactive. The apparatus further includes a bias circuit to receive the regulated voltage and generate one or more bias currents, which may be provided to an output circuit to output one or more bias outputs to one or more client circuits therefrom.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: May 17, 2016
    Assignee: Silicon Laboratories Inc.
    Inventors: Pavel Konecny, Dag Pettersen
  • Publication number: 20160126955
    Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.
    Type: Application
    Filed: January 11, 2016
    Publication date: May 5, 2016
    Inventors: Jinwen Xiao, Pavel Konecny, Axel Thomsen, Clayton Daigle, Xiaodong Wang, John Khoury, Alan Westwick, Shahram Tadayon
  • Patent number: 9236867
    Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: January 12, 2016
    Assignee: Silicon Laboratories Inc.
    Inventors: Jinwen Xiao, Pavel Konecny, Axel Thomsen, Clayton Daigle, Xiaodong Wang, John Khoury, Alan Westwick, Shahram Tadayon
  • Patent number: 9099994
    Abstract: In an embodiment, a method includes: during a first portion of a cycle of a clock signal generated by an oscillator, pre-charging a first capacitor of a first switched capacitor stage until a first comparator determines that a first node voltage of the first switched capacitor stage is greater than a first reference voltage at a first reference voltage node; applying a second reference voltage to the first reference voltage node; and responsive to a first edge of the clock signal, charging the first capacitor until the first comparator determines that the first node voltage is greater than the second reference voltage at the first reference voltage node.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 4, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Axel Thomsen, Pavel Konecny, Xiaodong Wang
  • Publication number: 20150180476
    Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.
    Type: Application
    Filed: October 31, 2014
    Publication date: June 25, 2015
    Inventors: Jinwen Xiao, Pavel Konecny, Axel Thomsen, Clayton Daigle, Xiaodong Wang, John Khoury, Alan Westwick, Shahram Tadayon
  • Patent number: 8880749
    Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.
    Type: Grant
    Filed: December 30, 2012
    Date of Patent: November 4, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Jinwen Xiao, Pavel Konecny, Axel Thomsen, Clayton Daigle, Xiaodong Wang, John Khoury, Alan Westwick, Shahram Tadayon
  • Publication number: 20140312820
    Abstract: An apparatus includes an integrated circuit (IC). The IC includes a differencing comparator. The differencing comparator receives a differential input signal. The differencing comparator compares the differential input signal to a threshold value. The differencing comparator includes a transconductance circuit coupled to receive the differential input signal and to provide a differential output signal.
    Type: Application
    Filed: June 16, 2014
    Publication date: October 23, 2014
    Inventors: Axel Thomsen, Kenneth W. Fernald, Pavel Konecny
  • Patent number: 8803360
    Abstract: Techniques are disclosed relating to supplying a power supply voltage to a gate driver. In one embodiment, an apparatus is disclosed that includes a first transistor configured to raise a voltage at a node and a second transistor configured to lower the voltage at the node. The apparatus further includes a first driver configured to receive a first power supply voltage, and to use the first power supply voltage to control a gate voltage of the first transistor. The apparatus further includes a second driver configured to receive a second power supply voltage, and to use the second power supply voltage to control a gate voltage of the second transistor. In such an embodiment, the apparatus includes a first regulator coupled to the first driver and configured to generate the first power supply voltage based on the second power supply voltage.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: August 12, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Pavel Konecny, Jinwen Xiao
  • Publication number: 20140176250
    Abstract: In an embodiment, a method includes: during a first portion of a cycle of a clock signal generated by an oscillator, pre-charging a first capacitor of a first switched capacitor stage until a first comparator determines that a first node voltage of the first switched capacitor stage is greater than a first reference voltage at a first reference voltage node; applying a second reference voltage to the first reference voltage node; and responsive to a first edge of the clock signal, charging the first capacitor until the first comparator determines that the first node voltage is greater than the second reference voltage at the first reference voltage node.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Inventors: Axel Thomsen, Pavel Konecny, Xiaodong Wang
  • Patent number: 8681026
    Abstract: An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: March 25, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Jinwen Xiao, Pavel Konecny, Axel Thomsen, Ka Y. Leung
  • Patent number: 8654484
    Abstract: A power supply including a switching voltage regulator detects a peak power fault if a peak power limit is exceeded during a switching cycle of the voltage regulator. A second fault condition exists if a second power limit, lower than the peak power limit, is exceeded over a second time period, longer than the first time period. The switching voltage regulator is stopped in response to either the first or the second fault condition. Responsive to the second fault condition, the switching voltage regulator may be stopped until AC power is cycled or until a predetermined time period has elapsed.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: February 18, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Pavel Konecny, Ali Fawaz
  • Publication number: 20140002184
    Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.
    Type: Application
    Filed: December 30, 2012
    Publication date: January 2, 2014
    Applicant: Silicon Laboratories Inc.
    Inventors: Jinwen Xiao, Pavel Konecny, Axel Thomsen, Clayton Daigle, Xiaodong Wang, John Khoury, Alan Westwick, Shahram Tadayon
  • Publication number: 20130222162
    Abstract: An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Inventors: Jinwen Xiao, Pavel Konecny, Axel Thomsen, Ka Y. Leung