Patents by Inventor Pavel Konecny

Pavel Konecny has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8508298
    Abstract: Techniques are disclosed relating to charging and discharging gates of transistors. In one embodiment, an apparatus includes first and second drivers. The first driver is configured to discharge a gate of a first transistor, and to send a charge indication to the second driver in response to reaching a Miller plateau for the first transistor. The second driver is configured to charge a gate of a second transistor above a threshold voltage in response to receiving the charge indication. In some embodiments, the second driver is configured to begin charging the gate of the second transistor to a voltage below the threshold voltage when the first driver begins discharging the gate of the first transistor begins, and to wait to charge the gate of the second transistor above the threshold voltage until the charge indication has been received.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: August 13, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Pavel Konecny, Jinwen Xiao
  • Patent number: 8493146
    Abstract: Techniques are disclosed relating to charging and discharging a gate of transistor. In one embodiment, an apparatus is disclosed that includes a driver configured to discharge a gate of a transistor. The driver is configured to discharge the gate at a first rate until reaching a Miller plateau for the transistor, and to discharge the gate at a second rate after reaching the Miller plateau. In such an embodiment, the first rate is greater than the second rate. In some embodiments, the driver is also configured to charge the gate of the transistor at a third rate until reaching a Miller plateau for the transistor, and to charge the gate at a fourth rate after reaching the Miller plateau, the third rate being greater than the fourth rate. In some embodiments, the apparatus is a class D amplifier.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: July 23, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Pavel Konecny, Jinwen Xiao, John M. Khoury
  • Publication number: 20120249099
    Abstract: Techniques are disclosed relating to supplying a power supply voltage to a gate driver. In one embodiment, an apparatus is disclosed that includes a first transistor configured to raise a voltage at a node and a second transistor configured to lower the voltage at the node. The apparatus further includes a first driver configured to receive a first power supply voltage, and to use the first power supply voltage to control a gate voltage of the first transistor. The apparatus further includes a second driver configured to receive a second power supply voltage, and to use the second power supply voltage to control a gate voltage of the second transistor. In such an embodiment, the apparatus includes a first regulator coupled to the first driver and configured to generate the first power supply voltage based on the second power supply voltage.
    Type: Application
    Filed: March 30, 2011
    Publication date: October 4, 2012
    Inventors: Pavel Konecny, Jinwen Xiao
  • Publication number: 20120229212
    Abstract: Techniques are disclosed relating to charging and discharging gates of transistors. In one embodiment, an apparatus includes first and second drivers. The first driver is configured to discharge a gate of a first transistor, and to send a charge indication to the second driver in response to reaching a Miller plateau for the first transistor. The second driver is configured to charge a gate of a second transistor above a threshold voltage in response to receiving the charge indication. In some embodiments, the second driver is configured to begin charging the gate of the second transistor to a voltage below the threshold voltage when the first driver begins discharging the gate of the first transistor begins, and to wait to charge the gate of the second transistor above the threshold voltage until the charge indication has been received.
    Type: Application
    Filed: March 10, 2011
    Publication date: September 13, 2012
    Inventors: Pavel Konecny, Jinwen Xiao
  • Publication number: 20120229211
    Abstract: Techniques are disclosed relating to charging and discharging a gate of transistor. In one embodiment, an apparatus is disclosed that includes a driver configured to discharge a gate of a transistor. The driver is configured to discharge the gate at a first rate until reaching a Miller plateau for the transistor, and to discharge the gate at a second rate after reaching the Miller plateau. In such an embodiment, the first rate is greater than the second rate. In some embodiments, the driver is also configured to charge the gate of the transistor at a third rate until reaching a Miller plateau for the transistor, and to charge the gate at a fourth rate after reaching the Miller plateau, the third rate being greater than the fourth rate. In some embodiments, the apparatus is a class D amplifier.
    Type: Application
    Filed: March 10, 2011
    Publication date: September 13, 2012
    Inventors: Pavel Konecny, Jinwen Xiao, John M. Khoury
  • Patent number: 8213192
    Abstract: A switching voltage regulator samples signals corresponding to a flyback voltage on an auxiliary winding on a primary side of the switching voltage regulator. The flyback voltage functions as feedback from the output voltage on the secondary side. On detection of presence of the flyback voltage, samples corresponding to the flyback voltage are stored until the flyback voltage falls below a threshold voltage. A history of N samples of the flyback voltage is thus maintained. A sample older than the most recently stored sample is used to generate control for generation of the output voltage of the switching voltage regulator. Use of the older sample ensures that the flyback voltage sample used is one that is close to, but before the current in the secondary winding goes to zero.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: July 3, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Pavel Konecny, Yeshoda Yedevelly
  • Publication number: 20120063037
    Abstract: A power supply including a switching voltage regulator detects a peak power fault if a peak power limit is exceeded during a switching cycle of the voltage regulator. A second fault condition exists if a second power limit, lower than the peak power limit, is exceeded over a second time period, longer than the first time period. The switching voltage regulator is stopped in response to either the first or the second fault condition. Responsive to the second fault condition, the switching voltage regulator may be stopped until AC power is cycled or until a predetermined time period has elapsed.
    Type: Application
    Filed: November 16, 2010
    Publication date: March 15, 2012
    Inventors: Pavel Konecny, Ali Fawaz
  • Patent number: 8041227
    Abstract: A communication device is disclosed having optical and near-field communication capability. The device includes an optical transceiver circuit fabricated on an integrated circuit die and configured to transmit and receive far field signals. A near field transceiver circuit is also fabricated on the integrated circuit die and is configured to transmit and receive near-field electro-magnetic signals. Control circuitry is provided to selectively enable the optical transceiver circuit and the near field transceiver circuit responsive to an external control signal.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: October 18, 2011
    Assignee: Silicon Laboratories Inc.
    Inventors: Wayne T. Holcombe, Pavel Konecny, Miroslav Svajda, Jean-Luc Nauleau, Robert Gordon Farmer
  • Publication number: 20110157919
    Abstract: A voltage across a capacitor provides a supply voltage for circuits in an integrated circuit used to control a switching voltage regulator. The capacitor is charged during an OFF portion of a pulse width modulated (PWM) control signal that controls a first transistor in the switching voltage regulator. The voltage across the capacitor is controlled to be between a high threshold and a low threshold. The voltage is controlled by comparing the voltage across the capacitor to a low threshold and charging the capacitor during the OFF portion of the PWM signal if the voltage across the capacitor is below the low threshold. The voltage across the capacitor is compared to a high threshold and the capacitor is not charged if the voltage across the capacitor is above the high threshold.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Inventors: Yeshoda Yedevelly, Pavel Konecny
  • Publication number: 20110157922
    Abstract: A switching voltage regulator samples signals corresponding to a flyback voltage on an auxiliary winding on a primary side of the switching voltage regulator. The flyback voltage functions as feedback from the output voltage on the secondary side. On detection of presence of the flyback voltage, samples corresponding to the flyback voltage are stored until the flyback voltage falls below a threshold voltage. A history of N samples of the flyback voltage is thus maintained. A sample older than the most recently stored sample is used to generate control for generation of the output voltage of the switching voltage regulator. Use of the older sample ensures that the flyback voltage sample used is one that is close to, but before the current in the secondary winding goes to zero.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Inventors: Pavel Konecny, Yeshoda Yedevelly
  • Publication number: 20110157941
    Abstract: A capacitor is charged synchronously with the beginning of an ON portion of a pulse width modulated (PWM) signal to generate a voltage across the capacitor using charging current sourced from an inductor on a primary side of a transformer. The voltage is supplied as a supply voltage to control circuitry in an integrated circuit used to generate the pulse width modulated signal. The charging is stopped when either the charging current goes above a predetermined charging current level or when the capacitor voltage goes above a predetermined capacitor voltage.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Inventors: Yeshoda Yedevelly, Pavel Konecny, Wayne T. Holcombe
  • Publication number: 20100021176
    Abstract: A communication device is disclosed having optical and near-field communication capability. The device includes an optical transceiver circuit fabricated on an integrated circuit die and configured to transmit and receive far field signals. A near field transceiver circuit is also fabricated on the integrated circuit die and is configured to transmit and receive near-field electro-magnetic signals. Control circuitry is provided to selectively enable the optical transceiver circuit and the near field transceiver circuit responsive to an external control signal.
    Type: Application
    Filed: November 15, 2007
    Publication date: January 28, 2010
    Applicant: Integration Associates Inc.
    Inventors: Wayne T. Holcombe, Pavel Konecny, Miroslav Svajda, Jean-Luc Nauleau, Robert Farmer
  • Patent number: 7644731
    Abstract: A gas valve having a valve member disposed within a valve cavity, and an elastomeric valve seat extending from a valve cavity wall into the valve cavity. The valve member is movable between an open position in which the valve member does not engage the resilient valve seat thereby permitting gas to flow through the gas valve, and a closed position in which the valve member does engage the resilient valve seat thereby preventing gas to flow through the gas valve. In some embodiments, the elastomeric valve seat extends radially into the valve cavity from a groove formed in the valve cavity wall.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: January 12, 2010
    Assignee: Honeywell International Inc.
    Inventors: Jiri Benda, Pavel Konecny
  • Patent number: 7624755
    Abstract: A gas valve may include a valve body and a valve member disposed within the valve body. A resilient sealing ring may be disposed within the valve body such that the valve member achieves a closed position when the valve member contacts the resilient sealing ring. In some instances, a gas valve may include both an upper resilient sealing ring and a lower resilient sealing ring. The upper resilient sealing ring and the lower resilient sealing ring may both permit overtravel.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: December 1, 2009
    Assignee: Honeywell International Inc.
    Inventors: Jiri Benda, Pavel Konecny
  • Publication number: 20080128037
    Abstract: A gas valve having a valve member disposed within a valve cavity, and an elastomeric valve seat extending from a valve cavity wall into the valve cavity. The valve member is movable between an open position in which the valve member does not engage the resilient valve seat thereby permitting gas to flow through the gas valve, and a closed position in which the valve member does engage the resilient valve seat thereby preventing gas to flow through the gas valve. In some embodiments, the elastomeric valve seat extends radially into the valve cavity from a groove formed in the valve cavity wall.
    Type: Application
    Filed: November 30, 2006
    Publication date: June 5, 2008
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Jiri Benda, Pavel Konecny
  • Publication number: 20070131286
    Abstract: A gas valve may include a valve body and a valve member disposed within the valve body. A resilient sealing ring may be disposed within the valve body such that the valve member achieves a closed position when the valve member contacts the resilient sealing ring. In some instances, a gas valve may include both an upper resilient sealing ring and a lower resilient sealing ring. The upper resilient sealing ring and the lower resilient sealing ring may both permit overtravel.
    Type: Application
    Filed: December 9, 2005
    Publication date: June 14, 2007
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Jiri Benda, Pavel Konecny
  • Publication number: 20040184598
    Abstract: A caller ID circuit is shown that uses resistors as a caller ID interface to a telephone line pair. The circuit includes a differential transconductance amplifier coupled to the telephone line pair using resistors and a common mode canceling transconductance amplifier coupled to the telephone line pair using the resistors. The invention also includes a gyrator transconductance amplifier coupled to the differential transconductance amplifier and the common mode canceling transconductance amplifier that is configured to generate an output current corresponding to a caller ID signal present at the telephone line pair. In a further refinement of the invention, the resistors are accurate resistors. In another refinement of the invention, the circuit further includes an analog to digital converter (ADC) coupled to the gyrator transconductance amplifier, where the ADC converts the output current from the gyrator transconductance amplifier into a pulse-width-modulated (PWM) signal.
    Type: Application
    Filed: February 20, 2004
    Publication date: September 23, 2004
    Applicant: Integration Associates Inc.
    Inventors: Wayne T. Holcombe, Pavel Konecny
  • Patent number: 6525592
    Abstract: The invention relates to an integrated high power sine wave carrier circuit for outputting a low distortion high power sine wave. The circuit is used for antennas, and especially for antennas in automotive appliances. The circuit comprises a H-bridge (2) with matched power transistors (4, 6, 8, 10), a sine generator (24) for driving the H-bridge and a regulator (22) for sensing the power applied to the antenna and controlling the current amplitude of the sine wave output by the sine generator. The circuit operates under partial time-working, whereby the integration circuit is turned on or off. The circuit therefore comprises a shutdown pin, for shutting the circuit down in order to allow cooling. The partial time operation allows the circuit to be integrated on a single die.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: February 25, 2003
    Assignee: AMI Semiconductor Belgium BVBA
    Inventors: Bernard Gilbert Guy Gentinne, Pavel Konecny, Ludek Pantucek
  • Publication number: 20020017945
    Abstract: The invention relates to an integrated high power sine wave carrier circuit for outputting a low distortion high power sine wave. The circuit is used for antennas, and especially for antennas in automotive appliances. The circuit comprises a H-bridge (2) with matched power transistors (4, 6, 8, 10), a sine generator (24) for driving the H-bridge and a regulator (22) for sensing the power applied to the antenna and controlling the current amplitude of the sine wave output by the sine generator. The circuit operates under partial time-working, whereby the integration circuit is turned on or off. The circuit therefore comprises a shutdown pin, for shutting the circuit down in order to allow cooling. The partial time operation allows the circuit to be integrated on a single die.
    Type: Application
    Filed: July 3, 2001
    Publication date: February 14, 2002
    Applicant: ALCATEL
    Inventors: Bernard Gilbert Guy Gentinne, Pavel Konecny, Ludek Pantucek
  • Patent number: 6339317
    Abstract: Regulator for a sine wave generator unit, including a load feeding power-bridge connected to an output of the sine wave generator. The regulator is inserted between a feedback output of the power-bridge and a reference voltage input of the sine wave generator. The regulator includes regulation means providing a power regulation signal (SET′) to the reference voltage input of the sine wave generator from a comparison between a signal (SENSE) at the feedback output of the power bridge and a predetermined set point signal (SETP′). The regulator (4′) is a proportional integrating differentiating regulator including start-up and/or shut-off envelope controlling means (19, 20, 21) associated to regulation means (14′, 17) for obtaining tightly controlled start-up and/or shut-off slope(s) of the signal at the load feeding output of the power bridge in addition to a tight control of the signal envelope between a start-up slope and the following shut-off slope.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: January 15, 2002
    Assignee: Alcatel
    Inventors: Bernard Gilbert Buy Gentinne, Aarnout Wieers, Pavel Konecny, Ludek Pantucek