Abstract: A desired pattern is formed in a photoresist layer that overlies a semiconductor wafer using a reflective mask. This mask is formed by consecutively depositing a reflective layer, an absorber layer and an anti-reflective (ARC) layer. The ARC layer is patterned according to the desired pattern. The ARC layer is inspected to find areas in which the desired pattern is not achieved. The ARC layer is then repaired to achieve the desired pattern with the absorber layer protecting the reflective layer. The desired pattern is transferred to the absorber layer to reveal the reflective portion of mask. Radiation is reflected off the reflective mask to the semiconductor wafer to expose the photoresist layer overlying the semiconductor wafer with the desired pattern.

Abstract: A desirable pattern is formed in a photoresist layer that overlies a semiconductor wafer using an attenuating phase shift reflective mask. This mask is formed by consecutively depositing an attenuating phase shift layer, a buffer layer and a repairable layer. The repairable layer is patterned according to the desirable pattern. The repairable layer is inspected to find areas in which the desirable pattern is not achieved. The repairable layer is then repaired to achieve the desirable pattern with the buffer layer protecting the attenuating phase shift layer. The desirable pattern is transferred to the buffer layer and then transferred to the attenuating phase shift layer to achieve the attenuating phase shift reflective mask. Radiation is reflected off the attenuating phase shift reflective mask to the photoresist layer to expose it with the desirable pattern.

Abstract: A desired pattern is formed in a photoresist layer that overlies a semiconductor wafer using a reflective mask. This mask is formed by consecutively depositing a reflective layer, an absorber layer and an anti-reflective (ARC) layer. The ARC layer is patterned according to the desired pattern. The ARC layer is inspected to find areas in which the desired pattern is not achieved. The ARC layer is then repaired to achieve the desired pattern with the absorber layer protecting the reflective layer. The desired pattern is transferred to the absorber layer to reveal the reflective portion of mask. Radiation is reflected off the reflective mask to the semiconductor wafer to expose the photoresist layer overlying the semiconductor wafer with the desired pattern.

Abstract: A desirable pattern is formed in a photoresist layer that overlies a semiconductor wafer using an attenuating phase shift reflective mask. This mask is formed by consecutively depositing an attenuating phase shift layer, a buffer layer and a repairable layer. The repairable layer is patterned according to the desirable pattern. The repairable layer is inspected to find areas in which the desirable pattern is not achieved. The repairable layer is then repaired to achieve the desirable pattern with the buffer layer protecting the attenuating phase shift layer. The desirable pattern is transferred to the buffer layer and then transferred to the attenuating phase shift layer to achieve the attenuating phase shift reflective mask. Radiation is reflected off the attenuating phase shift reflective mask to the photoresist layer to expose it with the desirable pattern.

Abstract: A stencil mask (12 or 12′) has both a thin membrane layer (106) and a stress controlled layer (104) for enabling electron and ion projection lithography at very small geometries. The thin membrane layer (106) is within a range of substantially forty to two hundred nanometers and is preferably silicon nitride, and the stress controlled layer is preferably a metal or a metal alloy. Annealing of the stress controlled layer (104) may be performed to obtain a desired stress characteristic. Semiconductors are made using the mask by projecting radiation through the thin membrane stencil mask and reduction optics (30) onto resist (44) formed on a plurality of die, the radiation forming a contrast image on the resist that is subsequently developed. Commercially available lithography equipment is compatible with the thin stencil mask.

Abstract: A method and apparatus for determining stress levels of membrane masks that may be used in membrane-based lithographic techniques is presented. A piezoelectric plate (30) is used to induce vibrations into the membrane mask (35), where the frequency and amplitude of the vibrations induced in the membrane layer (50) are optically sensed. By comparing the stimulus applied to the piezoelectric plate (30) with the response sensed optically in a gain phase analyzer (80), a frequency graph (110) associated with the membrane layer (50) is constructed such that resonant frequencies are easily determined. These resonant frequencies can then be used to calculate the stress associated with the membrane layer (50).