Abstract: Systems, apparatuses, and methods for implementing pixel wait synchronization techniques are disclosed. A system includes a host processor and a graphics processor which includes at least one graphics pipeline. During execution of a graphics application, the host processor determines that a second draw call is dependent on a first draw call. The host processor issues a wait sync event prior to issuing the second draw call to the graphics pipeline responsive to determining that the first draw call is still in-flight in the graphics pipeline. After the second draw call is issued to the graphics pipeline, the second draw call is processed by one or more stages of the graphics pipeline while the first draw call is still in-flight. The graphics pipeline stalls the second draw call at a given intermediate stage until a corresponding event counter equals a value specified by the wait sync event.

Abstract: Systems, apparatuses, and methods for managing a non-power of two memory configuration are disclosed. A computing system includes at least one or more clients, a control unit, and a memory subsystem with a non-power of two number of active memory channels. The control unit reduces a ratio of the number of active memory channels over the total number of physical memory channels to a ratio of a first number to a second number. If a first subset of physical address bits of a received memory request are greater than or equal to the first number, the control unit calculates a third number which is equal to a second subset of physical address bits modulo the first number and the control unit uses a concatenation of the third number and a third subset of physical address bits to select a memory channel for issuing the received memory request.

Abstract: Improvements in graphics processing pipelines are disclosed. The graphics processing pipeline processes graphics objects in a particular order (application programming interface order—“API order”) as requested by an application or other entity. However, certain components within the graphics processing pipeline, such as the pixel shader stage, may process those objects out of order. A technique is provided herein to allow the pixel shader stage to complete and export processed fragments out of order. The technique includes using a scoreboard to determine whether fragments ready to be exported from a pixel shader stage are the newest fragments in API order. If the fragments are the newest in API order, then the fragments are exported. If the fragments are not the newest in API order, then the fragments are discarded.

Abstract: Improvements in graphics processing pipelines are disclosed. The graphics processing pipeline processes graphics objects in a particular order (application programming interface order—“API order”) as requested by an application or other entity. However, certain components within the graphics processing pipeline, such as the pixel shader stage, may process those objects out of order. A technique is provided herein to allow the pixel shader stage to complete and export processed fragments out of order. The technique includes using a scoreboard to determine whether fragments ready to be exported from a pixel shader stage are the newest fragments in API order. If the fragments are the newest in API order, then the fragments are exported. If the fragments are not the newest in API order, then the fragments are discarded.

Abstract: A system, methods and apparatus perform remote access commands between nodes and allow preemption of context resources in an architecture such as Infiniband. The system detects an original request in a request queue for a data access task to access data from a first node to a second node and issues a first request from a first node to a second node. The first request requests the data access task be performed between the first node and the second node. The system receives, at the first node, a first response from the second node that partially completes the data access task. The system issues at least one subsidiary request from the first node to the second node to further complete the data access task between the first node and the second node. The subsidiary request(s) are based on an amount of partial completion of the data access task between the first node and the second node.

Abstract: A method and device for virtual memory support in a computer system using a mapping structure for address translation. Mapping indicators are associated with each process context and each mapping structure entry. When a context is demapped the mapping indicator associated with the context is changed and the mapping indicator in each mapping structure entry is employed to immediately invalidate further memory accesses for that context.

Abstract: A method and device for virtual memory support in a computer system using a mapping structure for address translation. Mapping indicators are associated with each process context and each mapping structure entry. When a context is demapped the mapping indicator associated with the context is changed and the mapping indicator in each mapping structure entry is employed to immediately invalidate further memory accesses for that context.