Abstract: A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure over the fin. The semiconductor device also includes a source region and a drain region in the fin and at opposite sides of the gate structure. The semiconductor device further includes a gate spacer on a sidewall of the gate structure. The gate spacer includes an air-gap spacer and a sealing spacer above the air-gap spacer, an upper portion of the gate structure is laterally overlapping with the sealing spacer, and the bottom portion of the gate structure is laterally overlapping with the air gap spacer.

Abstract: A semiconductor structure includes a first fin, which includes a first plurality of suspended nanostructures vertically stacked over one another, each of the first plurality of suspended nanostructure having a center portion that has a first cross section, and a second fin, which includes a second plurality of suspended nanostructures vertically stacked over one another, the first plurality of suspended nanostructures and the second plurality of suspended nanostructures having different material compositions, each of the second plurality of suspended nanostructure having a center portion that has a second cross section, wherein a shape or an area of the first cross section is different from that of the second cross section.

Abstract: Methods for manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate a substrate and channel layers vertically stacked over the substrate. The semiconductor structure also includes a dielectric fin structure formed adjacent to the channel layers and a gate structure abutting the channel layers and the dielectric fin structure. The semiconductor structure also includes a source/drain structure attached to the channel layers and a contact formed over the source/drain structure. The semiconductor structure also includes a Si layer covering a portion of a top surface of the source/drain structure. In addition, the Si layer is sandwiched between the dielectric fin structure and the contact.

Abstract: A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure formed across the fin. The semiconductor device also includes a gate spacer formed over a sidewall of the gate structure. The gate spacer includes a sidewall spacer and a sealing spacer formed above the sidewall spacer. In addition, an air gap is vertically sandwiched between the sidewall spacer and the sealing spacer. The semiconductor device further includes a hard mask formed over the gate structure and covering a sidewall of the sealing spacer.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.

Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor device includes a fin protruding from a substrate and an isolation structure surrounding the fin. The semiconductor device also includes a first channel layer and a second channel layer formed over the fin and at least partially overlapping the isolation structure. The semiconductor device further includes a gate structure formed in a space between the first channel layer and the second channel layer and wrapping around the first channel layer and the second channel layer.

Abstract: A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.

Abstract: Methods for manufacturing a semiconductor structure is provided. The method for manufacturing the semiconductor structure includes forming nanowire structures over a substrate and forming a gate structure across nanowire structures. The method for manufacturing the semiconductor structure also includes forming a source/drain structure adjacent to the gate structure and forming a Si layer over the source/drain structure. The method for manufacturing the semiconductor structure also includes forming a SiGe layer over the Si layer and oxidizing the SiGe layer to form an oxide layer. The method for manufacturing the semiconductor structure also includes forming a contact through the Si layer over the source/drain structure.

Abstract: Provided is a semiconductor device including a semiconductor substrate, a plurality of semiconductor nanosheets, a plurality of source/drain (S/D) features and a gate stack. The semiconductor substrate includes a first fin and a second fin. The first fin has a first width less than a second width of the second fin, and a top surface of the first fin is lower than a top surface of the second fin. The plurality of semiconductor nanosheets are disposed on the first fin and the second fin. The plurality of source/drain (S/D) features are located on the first fin and the second fin and abutting the plurality of semiconductor nanosheets. The gate stack wraps each of the plurality of semiconductor nanosheets.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor fin over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, first and second dielectric layers over the substrate, and an S/D contact disposed on the epitaxial S/D feature. The first and second dielectric layers have different material compositions. A first sidewall of the epitaxial S/D feature is facing the first dielectric layer, a second sidewall of the epitaxial S/D feature is facing the second dielectric layer, and the S/D contact partially covers a top surface of the epitaxial S/D feature and extends continuously to cover the first sidewall of the epitaxial S/D feature.

Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a fin protruding from a substrate and forming an isolation structure surrounding the fin. The method also includes epitaxially growing channel fins on sidewalls of the fin over the isolation structure and etching the fin to form a space between the channel fins. The method further includes forming a gate structure to fill the space between the channel fins.

Abstract: A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.

Abstract: Provided is a method of manufacturing a semiconductor device including providing a semiconductor substrate, and forming an epitaxial stack on the semiconductor substrate. The epitaxial stack comprises a plurality of first epitaxial layers interposed by a plurality of second epitaxial layers. The method further includes patterning the epitaxial stack and the semiconductor substrate to form a semiconductor fin, recessing a portion of the semiconductor fin to form source/drain spaces; and laterally removing portions of the plurality of first epitaxial layers exposed by the source/drain spaces to form a plurality of cavities. The method further includes forming inner spacers in the plurality of cavities, performing a treatment process to remove an inner spacer residue in the source/drain spaces, forming S/D features in the source/drain spaces, and forming a gate structure engaging the semiconductor fin.

Abstract: The present disclosure provides a method of semiconductor fabrication. The method includes forming a fin protruding from a substrate, the fin having a first sidewall and a second sidewall opposing the first sidewall; forming a sacrificial dielectric layer on the first and second sidewalls and a top surface of the fin; etching the sacrificial dielectric layer to remove the sacrificial dielectric layer from the second sidewall of the fin; forming a recess in the fin; growing an epitaxial source/drain (S/D) feature from the recess, the epitaxial S/D feature having a first sidewall and a second sidewall opposing the first sidewall, wherein the sacrificial dielectric layer covers the first sidewall of the epitaxial S/D feature; recessing the sacrificial dielectric layer, thereby exposing the first sidewall of the epitaxial S/D feature; and forming an S/D contact on the first sidewall of the epitaxial S/D feature.

Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.

Abstract: A semiconductor device includes a semiconductor substrate having a fin structure, a gate stack across the fin structure, a spacer structure on a sidewall of the gate stack, an epitaxial structure on the semiconductor substrate, and a dielectric structure in the spacer structure. The dielectric structure extends along a lower portion of the spacer structure and across the fin structure.

Abstract: A semiconductor device according to the present disclosure includes first gate-all-around (GAA) devices in a first device area and second GAA devices in a second device area. Each of the first GAA devices includes a first vertical stack of channel members, a first gate structure over and around the first vertical stack of channel members, and a plurality of inner spacer features. Each of the second GAA devices includes a second vertical stack of channel members and a second gate structure over and around the second vertical stack of channel members. Two adjacent channel members of the first vertical stack of channel members are separated by a portion of the first gate structure and at least one of the plurality of inner spacer features. Two adjacent channel members of the second vertical stack of channel members are separated only by a portion of the second gate structure.