Patents by Inventor Pei-Hua Wang

Pei-Hua Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250098300
    Abstract: A display device includes a substrate, an insulating layer and a metal layer. The substrate includes a light transmitting region. The insulating layer is disposed on the substrate and between the substrate and the metal layer. An edge of the insulating layer has a concave corner, and the concave corner is recessed toward the metal layer and located in the light transmitting region. A manufacturing method of the display device is also proposed.
    Type: Application
    Filed: December 28, 2023
    Publication date: March 20, 2025
    Inventors: HSIN-HUA TSAI, Pei-Yun WANG
  • Patent number: 12238913
    Abstract: Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: February 25, 2025
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Juan G. Alzate-Vinasco, Fatih Hamzaoglu, Bernhard Sell, Pei-hua Wang, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Umut Arslan, Travis W. Lajoie, Chieh-jen Ku
  • Publication number: 20250019459
    Abstract: The present disclosure relates to antibodies and antibody derivatives that bind to MSLN and methods of using the same. In certain embodiments, the antibody or antibody derivative disclosed herein comprises a single domain antibody that binds to MSLN.
    Type: Application
    Filed: September 23, 2024
    Publication date: January 16, 2025
    Inventors: Pei-Hua LIN, Wei-Dong JIANG, Wenfeng XU, Hassan ISSAFRAS, Chi-Ling TSENG, Jiin-Tarng WANG
  • Patent number: 12176284
    Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: December 24, 2024
    Assignee: Intel Corporation
    Inventors: Travis Lajoie, Abhishek Sharma, Juan Alzate-Vinasco, Chieh-Jen Ku, Shem Ogadhoh, Allen Gardiner, Blake Lin, Yih Wang, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani
  • Patent number: 12150297
    Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Noriyuki Sato, Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku, Arnab Sen Gupta, Matthew V. Metz, Elliot N. Tan, Hui Jae Yoo, Travis W. Lajoie, Van H. Le, Pei-Hua Wang
  • Patent number: 12139817
    Abstract: Methods are provided for multiplexed amplification of selected targets and analysis of the amplified targets. In preferred aspects the amplification and analysis take place on the same solid support and preferably in a localized area such as a bead or a feature of an array. In preferred aspects the analysis is a determination of sequence at one or more locations in the amplified target. The methods may be used for genotyping, sequencing and analysis of copy number.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: November 12, 2024
    Assignee: AFFYMETRIX, INC.
    Inventors: Glenn Fu, Michael Shapero, Pei-Hua Wang
  • Patent number: 12080643
    Abstract: Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 3, 2024
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Juan G. Alzate Vinasco, Chieh-Jen Ku, Shem O. Ogadhoh, Allen B. Gardiner, Blake C. Lin, Yih Wang, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani
  • Patent number: 12080781
    Abstract: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: September 3, 2024
    Assignee: Intel Corporation
    Inventors: Noriyuki Sato, Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku, Elliot N. Tan, Hui Jae Yoo, Travis W. Lajoie, Van H. Le, Pei-Hua Wang, Jason Peck, Tobias Brown-Heft
  • Publication number: 20240234579
    Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.
    Type: Application
    Filed: February 16, 2024
    Publication date: July 11, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Arnab Sen Gupta, Travis W. LaJoie, Sarah Atanasov, Chieh-Jen Ku, Bernhard Sell, Noriyuki Sato, Van Le, Matthew Metz, Hui Jae Yoo, Pei-Hua Wang
  • Publication number: 20240164795
    Abstract: A surgical instrument includes a rod and a push portion. The push portion includes a first end connected to an end of the rod and a second end having a blade portion. The push portion includes a plurality of grooves. The plurality of grooves is recessed in a surface of the push portion and is spaced from each other. Each two adjacent grooves has a rib formed therebetween. A top face of a cross section of each rib is the surface of the push portion. Each rib has a guiding face on the cross section of the push portion. The guiding face is connected to the surface of the push portion. The guiding face faces a rotating direction of the rod. An angle between the guiding face and the surface of the push portion in the cross section is greater than 90°.
    Type: Application
    Filed: November 22, 2022
    Publication date: May 23, 2024
    Inventors: Tung-Lin TSAI, Chun-Chieh TSENG, Chun-Ming CHEN, Yue-Jun WANG, Pei-Hua WANG
  • Patent number: 11991873
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Julie Rollins, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Yu-Wen Huang, Shu Zhou
  • Patent number: 11955560
    Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Arnab Sen Gupta, Travis W. LaJoie, Sarah Atanasov, Chieh-Jen Ku, Bernhard Sell, Noriyuki Sato, Van Le, Matthew Metz, Hui Jae Yoo, Pei-Hua Wang
  • Patent number: 11950407
    Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Juan G. Alzate Vinasco, Travis W. Lajoie, Abhishek A. Sharma, Kimberly L Pierce, Elliot N. Tan, Yu-Jin Chen, Van H. Le, Pei-Hua Wang, Bernhard Sell
  • Patent number: 11929415
    Abstract: A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Pei-Hua Wang, Bernhard Sell, Travis W. Lajoie
  • Patent number: 11908911
    Abstract: A device is disclosed. The device includes a source contact in a source contact trench and a drain contact in a drain contact trench, a channel under the source contact and the drain contact, a first spacing layer on a bottom of the source contact trench and a second spacing layer on a bottom of the drain contact trench. The first spacing layer and the second spacing layer are on the surface of the channel. The device also includes a gate electrode below the channel and a dielectric above the gate electrode and underneath the channel.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Bernhard Sell, Pei-Hua Wang
  • Publication number: 20240049450
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Gregory GEORGE, Akash GARG, Allen B. GARDINER, Shem OGADHOH, Juan G. ALZATE VINASCO, Umut ARSLAN, Fatih HAMZAOGLU, Nikhil MEHTA, Jared STOEGER, Yu-Wen HUANG, Shu ZHOU
  • Patent number: 11832438
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Jared Stoeger, Yu-Wen Huang, Shu Zhou
  • Patent number: 11810980
    Abstract: Embodiments herein describe techniques for a transistor above a substrate. The transistor includes a channel layer above the substrate. The channel layer includes a first channel material of a first conductivity. In addition, the channel layer further includes elements of one or more additional materials distributed within the channel layer. The channel layer including the elements of the one or more additional materials has a second conductivity different from the first conductivity. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 7, 2023
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Pei-Hua Wang, Bernhard Sell, Martin M. Mitan, Leonard C. Pipes
  • Patent number: 11784088
    Abstract: Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Bernhard Sell, Pei-Hua Wang, Harish Ganapathy, Leonard C. Pipes
  • Patent number: 11758711
    Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Yih Wang, Abhishek A. Sharma, Tahir Ghani, Allen B. Gardiner, Travis W. Lajoie, Pei-Hua Wang, Chieh-Jen Ku, Bernhard Sell, Juan G. Alzate-Vinasco, Blake C. Lin