Abstract: Operating method, memory system, and control circuit are provided. The operating method is for operating a memory device comprising a selector and a memory element serially coupled to the selector. The operating method comprises presetting the memory device by providing a preset signal to the memory device, wherein the preset signal is clamped at a first current; and accessing the memory device by providing an access signal to the memory device, wherein a second current greater than the first current flows through the memory device when the access signal is provided to the memory device.

Abstract: A ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, a ferroelectric composite layer disposed between the first electrode and the second electrode, and a first insulating layer disposed on one side of the ferroelectric composite layer. The ferroelectric composite layer includes a first electrode layer, a second electrode layer, a ferroelectric layer and an antiferroelectric layer. The first electrode layer is opposite to the second electrode layer, and the ferroelectric layer and the antiferroelectric layer are disposed between the first electrode layer and the second electrode layer.

Abstract: A semiconductor structure including a substrate, a conductive layer, and a semiconductor device is provided. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface toward the second surface, and a through hole passing through the substrate. The conductive layer fills in the through hole. The semiconductor device is disposed on the second surface and is electrically connected to the conductive layer, and the at least one insulating vacancy is distributed corresponding to the semiconductor device.

Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, a ferroelectric composite layer disposed between the first electrode and the second electrode, and a first insulating layer disposed on one side of the ferroelectric composite layer.

Abstract: A structure of an electrochemical unit includes a substrate, a first metal layer disposed on the substrate, and an array of electrochemical cells disposed on the first metal layer. The array of the electrochemical cells includes a plurality of electrochemical cells. Each of the electrochemical cells includes the first metal layer disposed on the substrate, a first electrode disposed on the first metal layer, a polymer layer disposed on the substrate and adjacent to the first metal layer and the first electrode. A second metal layer is disposed on the polymer layer, and a second electrode is disposed on the second metal layer. A pore is constituted between the polymer layers of every the two electrochemical cells. A cavity located above the first electrode is defined between every the two electrochemical cells, wherein the cavity is communicated with the pore.

Abstract: A liquid-sensing apparatus includes a substrate, partitions, and independent sensors. The partitions are disposed on the substrate for separating several housing spaces in order to respectively house a to-be-detected liquid, wherein each of the housing spaces has a bottom, a closed sidewall, and an open top, and thus the to-be-detected liquid may be dripped from the top of the housing space. The independent sensors are respectively formed at the bottom of different housing spaces, wherein the independent sensors respectively include different sensing material layers, and surfaces of the different sensing material layers have nanoholes.

Abstract: A liquid-sensing apparatus includes a substrate, partitions, and independent sensors. The partitions are disposed on the substrate for separating several housing spaces in order to respectively house a to-be-detected liquid, wherein each of the housing spaces has a bottom, a closed sidewall, and an open top, and thus the to-be-detected liquid may be dripped from the top of the housing space. The independent sensors are respectively formed at the bottom of different housing spaces, wherein the independent sensors respectively include different sensing material layers, and surfaces of the different sensing material layers have nanoholes.

Abstract: A structure of an electrochemical unit includes a substrate, a first metal layer disposed on the substrate, and an array of electrochemical cells disposed on the first metal layer. The array of the electrochemical cells includes a plurality of electrochemical cells. Each of the electrochemical cells includes the first metal layer disposed on the substrate, a first electrode disposed on the first metal layer, a polymer layer disposed on the substrate and adjacent to the first metal layer and the first electrode. A second metal layer is disposed on the polymer layer, and a second electrode is disposed on the second metal layer. A pore is constituted between the polymer layers of every the two electrochemical cells. A cavity located above the first electrode is defined between every the two electrochemical cells, wherein the cavity is communicated with the pore.

Abstract: A structure of an electrochemical unit includes a substrate, a first metal layer disposed on the substrate, and an array of electrochemical cells disposed on the first metal layer. The array of the electrochemical cells includes a plurality of electrochemical cells. Each of the electrochemical cells includes the first metal layer disposed on the substrate, a first electrode disposed on the first metal layer, a polymer layer disposed on the substrate and adjacent to the first metal layer and the first electrode. A second metal layer is disposed on the polymer layer, and a second electrode is disposed on the second metal layer. A pore is constituted between the polymer layers of every the two electrochemical cells. A cavity located above the first electrode is defined between every the two electrochemical cells, wherein the cavity is communicated with the pore.

Abstract: The disclosure provides a sensing device including a supporting member, a thermal resistance portion, a sensing unit and a heating unit. The supporting member has a supporting surface. The thermal resistance portion is located within the supporting member, wherein a thermal conductivity of the thermal resistance portion is less than a thermal conductivity of the supporting member. The sensing unit is disposed on the supporting surface. The heating unit is disposed on the supporting surface, wherein the heating unit is configured to heat the sensing unit, and an orthogonal projection of the heating unit on the supporting surface overlaps an orthogonal projection of the thermal resistance portion on the supporting surface. In addition, the disclosure also provides a method for manufacturing the sensing device.

Abstract: A structure of an electrochemical unit includes a substrate, a first metal layer disposed on the substrate, and an array of electrochemical cells disposed on the first metal layer. The array of the electrochemical cells includes a plurality of electrochemical cells. Each of the electrochemical cells includes the first metal layer disposed on the substrate, a first electrode disposed on the first metal layer, a polymer layer disposed on the substrate and adjacent to the first metal layer and the first electrode. A second metal layer is disposed on the polymer layer, and a second electrode is disposed on the second metal layer. A pore is constituted between the polymer layers of every the two electrochemical cells. A cavity located above the first electrode is defined between every the two electrochemical cells, wherein the cavity is communicated with the pore.

Abstract: A bonding structure including a first substrate, a second substrate, and an adhesive layer is provided. The first substrate has a plurality of first trenches. The adhesive layer is located between the first substrate and the second substrate, and the first trenches are filled with the adhesive layer.

Abstract: A bonding structure including a first substrate, a second substrate, and an adhesive layer is provided. The first substrate has a plurality of first trenches. The adhesive layer is located between the first substrate and the second substrate, and the first trenches are filled with the adhesive layer.

Abstract: The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

Abstract: The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

Abstract: A dual damascene structure having a through silicon via and a manufacturing method thereof are provided. The method includes forming a first, a second, and a third dielectric layers a on a substrate having a conductive structure. A trench is formed in the third dielectric layer. A hard mask layer is formed on the third dielectric layer and a surface of the trench. A first opening having a tapered sidewall is formed in the hard mask layer. A second opening is formed in the second and the third dielectric layers. The substrate exposed by the second opening and the first opening is etched to form a through hole so as to form a dual damascene opening. A liner layer is formed on a surface of the dual damascene opening and the conductive structure is exposed. The dual damascene opening is filled with a conductive material.

Abstract: The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

Abstract: A trench capacitor structure is provided. The trench capacitor structure includes a substrate, a trench formed in the substrate, a plurality of scallops formed in the sidewalls of the trench, and at least one capacitor formed within at least one of the scallops. The disclosure also provides a method of manufacturing the trench capacitor structure.

Abstract: The present invention relates to a charge trapping device and a method for manufacturing the same. The charge trapping device includes: a substrate having a first surface and an opposite second surface; a tunneling insulating layer, disposed on the first surface of the substrate; a charge trapping layer, disposed on the tunneling insulating layer and including a first dielectric layer and a second dielectric layer, in which the first dielectric layer is connected to the tunneling insulating layer, the second dielectric layer is disposed over the first dielectric layer, and a conduction band offset between the first dielectric layer and the substrate is larger than that between the second dielectric layer and the substrate; and a blocking insulating layer, disposed on the charge trapping layer and connected to the second dielectric layer. Accordingly, the charge trapping device of the present invention has excellent programming, and erasing and charge retention properties.

Abstract: A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to form a patterned second mask layer in a predetermined region for formation of a capacitor. A plurality of hemispherical grain structures are formed on a sidewall of the patterned second mask layer. The first mask layer is etched by using the hemispherical grain structures and the patterned second mask layer as a mask, thereby forming a patterned first mask layer having a pattern. The pattern of the first mask layer is transferred to the bottom electrode material layer. And, a capacitor dielectric layer and a top electrode layer are formed on the bottom electrode material layer to form the capacitor.