Patents by Inventor Pei Lu

Pei Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11928132
    Abstract: Provided are a database processing method and apparatus, and a computer readable storage medium. The database processing method comprises: after a lock wait is generated, writing lock wait related information into a lock wait log.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 12, 2024
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD.
    Inventors: Pin Lin, Yan Ding, Qinyuan Lu, Chen Qi, Yifang Yu, Pei Zhao
  • Patent number: 11908794
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu
  • Publication number: 20240055496
    Abstract: A semiconductor structure includes a substrate, at least one gate electrode, a plurality of source/drain (S/D) regions, a backside contact, a first dielectric layer, and a conductive via. The at least one gate electrode is disposed in the substrate. The S/D regions is disposed in the substrate and laterally disposed aside the at least one gate electrode. The backside contact is disposed above the S/D regions and the at least one gate electrode. The first dielectric layer is disposed between the backside contact and the plurality of S/D regions and the at least one gate electrode. The conductive via is extended through the first dielectric layer to electrically connect the S/D regions and the backside contact. The conductive via includes an anisotropic transport material or a topological material.
    Type: Application
    Filed: August 14, 2022
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Pei Lu, Shin-Yi Yang, Yun-Chi Chiang, Han-Tang Hung, Cian-Yu Chen, Ming-Han Lee
  • Publication number: 20240055352
    Abstract: A semiconductor device includes a dielectric structure, a conductive structure disposed in the dielectric structure, a first dielectric feature disposed over the dielectric structure, a conductive element disposed in the first dielectric feature and connected to the conductive structure, and a barrier feature disposed around the conductive element and disposed outside of the conductive structure.
    Type: Application
    Filed: August 10, 2022
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cian-Yu CHEN, Shin-Yi YANG, Ching-Fu YEH, Meng-Pei LU, Chin-Lung CHUNG, Yun-Chi CHIANG, Ming-Han LEE
  • Publication number: 20230387019
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and is adjacent to the first conductive feature. The first and second conductive features are separated by a cavity. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the cavity and further extends along opposing sidewalls of the first and second conductive features. A dielectric cap covers and seals the cavity. The dielectric cap has a top surface that is approximately planar with top surfaces of the first and second conductive features. The first conductive feature and the second conductive feature comprise graphene intercalated with one or more metals.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 30, 2023
    Inventors: Shin-Yi Yang, Meng-Pei Lu, Chin-Lung Chung, Ming-Han Lee, Shau-Lin Shue
  • Publication number: 20230387239
    Abstract: A semiconductor device includes a substrate, a plurality of channel layers, two epitaxial structures, a conductive structure, a via, and a graphene barrier. The channel layers and the epitaxial structures are disposed over the substrate. The channel layers are connected between the epitaxial structures. The conductive structure is disposed on the substrate opposite to the epitaxial structures. The via is connected between one of the epitaxial structure and the conductive structure. The graphene barrier surrounds the via.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Yi YANG, Meng-Pei LU, Han-Tang HUNG, Ching-Fu YEH, Ming-Han LEE, Shau-Lin SHUE
  • Publication number: 20230378067
    Abstract: A semiconductor structure includes a substrate, a dielectric layer, and a graphene conductive structure. The dielectric layer is disposed on the substrate, and has an inner lateral surface that is perpendicular to the substrate. The graphene conductive structure is formed in the dielectric layer and has at least one graphene layer extending in a direction parallel to the inner lateral surface of the dielectric layer.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsu-Chun KUO, Shin-Yi YANG, Yu-Chen CHAN, Shu-Wei LI, Meng-Pei LU, Ming-Han LEE
  • Patent number: 11816840
    Abstract: A method, an apparatus, a device, and a storage medium for extracting a cardiovascular vessel from a CTA image, the method including the steps of: performing erosion operation and dilation operation on image data successively via a preset structural element to obtain a structure mask; performing a slice-by-slice transformation on the plane of section images of the structural mask to acquire the first ascending aortic structure in the structural mask, and acquiring an aortic center position and an aortic radius in the last slice of the plane of section image of the said structural mask; establishing a binarized sphere structure according to the aortic center position and the aortic radius, and synthesizing a second ascending aorta structure by combining the first ascending aorta structure with the structure mask and the binarized sphere structure.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: November 14, 2023
    Assignee: Shenzhen Institutes of Advanced Technology
    Inventors: Shoujun Zhou, Baochang Zhang, Baolin Li, Cheng Wang, Pei Lu
  • Publication number: 20230352409
    Abstract: A semiconductor device includes a substrate and an interconnect layer disposed on the substrate. The interconnect layer includes a dielectric layer and an interconnect extending through the dielectric layer. The interconnect includes a bulk metal region and a single barrier/liner layer, which serves as both a barrier layer and a liner layer and which is disposed to separate the bulk metal region from the dielectric layer.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Pei LU, Shin-Yi YANG, Ching-Fu YEH, Chin-Lung CHUNG, Cian-Yu CHEN, Yun-Chi CHIANG, Tsu-Chun KUO, Ming-Han LEE
  • Publication number: 20230326857
    Abstract: A semiconductor device includes a substrate and an interconnect layer disposed over the substrate. The interconnect layer includes an interconnect structure which includes a topological material. The topological material includes a topological insulator, a topological semimetal, or a combination thereof. A method for manufacturing the semiconductor device is also disclosed.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Pei LU, Shin-Yi YANG, Cian-Yu CHEN, Yun-Chi CHIANG, Ming-Han LEE
  • Publication number: 20230290694
    Abstract: A test key configured to measure resistance of a through semiconductor via in a semiconductor substrate is provided. The test key includes a first resistor, a first conductor, a first probe pad, a second conductor, a second probe pad, a third conductor, a third probe pad, a fourth conductor, and a fourth probe pad. The first probe pad is electrically connected to a first end of the through semiconductor via by the first resistor and the first conductor. The second probe pad is electrically connected to the first end of the through semiconductor via by the second conductor. The third probe pad is electrically connected to a second end of the through semiconductor via by the third conductor. The fourth probe pad is electrically connected to the second end of the through semiconductor via by the fourth conductor.
    Type: Application
    Filed: March 14, 2022
    Publication date: September 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tse-Pan Yang, Wei Lee, Kuo-Pei Lu, Jen-Yuan Chang
  • Patent number: 11682616
    Abstract: A semiconductor structure includes a substrate, a plurality of conductive features disposed over the substrate, and an isolation structure between conductive features and separating the conductive features from each other. Each of the conductive features includes a first metal layer and a 2D material layer. Another semiconductor structure includes a first conductive feature, a dielectric structure over the first conductive feature, a second conductive feature in the dielectric structure and coupled to the first conductive feature, and a conductive line over and coupled to the second conductive feature. In some embodiments, the conductive line includes a first 3D material layer, a first 2D material layer, and a second 3D material layer. The first 2D material layer is disposed between the first 3D material layer and the second 3D material layer.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Pei Lu, Shin-Yi Yang, Shu-Wei Li, Chin-Lung Chung, Ming-Han Lee
  • Publication number: 20230066891
    Abstract: A semiconductor structure includes a substrate, a dielectric layer, and a graphene conductive structure. The dielectric layer is disposed on the substrate, and has an inner lateral surface that is perpendicular to the substrate. The graphene conductive structure is formed in the dielectric layer and has at least one graphene layer extending in a direction parallel to the inner lateral surface of the dielectric layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsu-Chun KUO, Shin-Yi YANG, Yu-Chen CHAN, Shu-Wei LI, Meng-Pei LU, Ming-Han LEE
  • Publication number: 20230037554
    Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure comprises at least one two-dimensional (2D) conductive structure; a dielectric layer disposed on the 2D conductive structure; and at least one interconnect structure disposed in the dielectric layer and extending into the 2D conductive structure, wherein the interconnect structure laterally connects to at least one edge of the 2D conductive structure.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 9, 2023
    Inventors: SHU-WEI LI, YU-CHEN CHAN, MENG-PEI LU, SHIN-YI YANG, MING-HAN LEE
  • Patent number: 11551967
    Abstract: Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Pei Lu, Ming-Han Lee, Shin-Yi Yang, Tz-Jun Kuo
  • Publication number: 20220359378
    Abstract: A method for forming a semiconductor structure includes following operations. A hybrid layered structure is formed. The hybrid layered structure includes at least a 2D material layer and a first 3D material layer. Portions of the hybrid layered structure are removed to form a plurality of conductive features and at least an opening between the conductive features. A dielectric material is formed to fill the opening and to form an air gap sealed within.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: MENG-PEI LU, SHIN-YI YANG, SHU-WEI LI, CHIN-LUNG CHUNG, MING-HAN LEE
  • Publication number: 20220359413
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and is adjacent to the first conductive feature. The first and second conductive features are separated by a cavity. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the cavity and further extends along opposing sidewalls of the first and second conductive features. A dielectric cap covers and seals the cavity. The dielectric cap has a top surface that is approximately planar with top surfaces of the first and second conductive features. The first conductive feature and the second conductive feature comprise graphene intercalated with one or more metals.
    Type: Application
    Filed: May 5, 2021
    Publication date: November 10, 2022
    Inventors: Shin-Yi Yang, Meng-Pei Lu, Chin-Lung Chung, Ming-Han Lee, Shau-Lin Shue
  • Publication number: 20220352012
    Abstract: Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.
    Type: Application
    Filed: July 19, 2022
    Publication date: November 3, 2022
    Inventors: Meng-Pei LU, Tz-Jun Kuo, Shin-Yi Yang, Ming-Han Lee
  • Patent number: D971251
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: November 29, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Pei Lu, Tsu-Yi Ren
  • Patent number: D978902
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: February 21, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Pei Lu, Tsu-Yi Ren