Patents by Inventor Pei-Ming Chen
Pei-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240144467Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
-
Publication number: 20240114989Abstract: An upper for an article of footwear is configured to be connected to a sole structure and is configured to receive a foot. The upper includes a knitted component having a strobel portion that is configured to be disposed underneath the foot. The strobel portion defines an interior surface and an exterior surface of the knitted component. The strobel portion defines a strobel passage between the interior surface and the exterior surface. Also, the upper includes a tensile strand that extends through the strobel passage.Type: ApplicationFiled: December 15, 2023Publication date: April 11, 2024Inventors: Daniel A. Podhajny, Chung-Ming Chang, Ya-Fang Chen, Pei-Ju Su
-
Publication number: 20230230978Abstract: A sensing device has a sensing area, a pad area, and a peripheral area, and the pad area is located between the sensing area and the peripheral area, including: a sensing element, a pad, and a metal strip. The sensing element is located in the sensing area. The pad is located in the pad area and electrically connected to the sensing element. The metal strip is located in the peripheral area, and an extending direction of the metal strip is parallel to an extending direction of the pad.Type: ApplicationFiled: August 8, 2022Publication date: July 20, 2023Applicant: AUO CorporationInventors: Te-Chun Huang, Pei-Ming Chen
-
Patent number: 11181787Abstract: A touch apparatus includes a substrate, a plurality of pixel structures, a first touch electrode, a second touch electrode, a third touch electrode and a first conductive pattern. The first touch electrode and the second touch electrode are located at a first side of a transparent window. The third touch electrode is located at a second side of the transparent window. The first touch electrode, the second touch electrode and the third touch electrode are sequentially arranged in a first direction. A main portion of the first conductive pattern is electrically connected to the first touch electrode. The main portion of the first conductive pattern overlaps with the second touch electrode and is electrically isolated from the second touch electrode. A dummy portion of the first conductive pattern is electrically connected to the third touch electrode and structurally separated from the main portion of the first conductive pattern.Type: GrantFiled: September 17, 2019Date of Patent: November 23, 2021Assignee: Au Optronics CorporationInventors: Hsun-Chen Chu, Pei-Ming Chen
-
Patent number: 11068093Abstract: A touch display panel is provided, including a common electrode ring, a first and a second common electrode pattern, pixel structures, an edge common signal line, and common signal lines disposed on a substrate. The first and second common electrode patterns and the pixel structures are located in a region surrounded by the common electrode ring. The first common electrode pattern is spaced from the second common electrode pattern by a gap. The first and the second common electrode patterns respectively overlap some of the pixel structures. The edge common signal line is disposed on the substrate, traces along the gap, and extends toward the common electrode ring to be electrically connected to the common electrode ring. The first common electrode pattern overlaps and is electrically connected to one common signal line. The second common electrode pattern overlaps and is electrically connected to another common signal line.Type: GrantFiled: October 8, 2019Date of Patent: July 20, 2021Assignee: Au Optronics CorporationInventors: Te-Chun Huang, Wen-Yi Hsu, Zeng-De Chen, Pei-Ming Chen
-
Publication number: 20200393711Abstract: A touch apparatus includes a substrate, a plurality of pixel structures, a first touch electrode, a second touch electrode, a third touch electrode and a first conductive pattern. The first touch electrode and the second touch electrode are located at a first side of a transparent window. The third touch electrode is located at a second side of the transparent window. The first touch electrode, the second touch electrode and the third touch electrode are sequentially arranged in a first direction. A main portion of the first conductive pattern is electrically connected to the first touch electrode. The main portion of the first conductive pattern overlaps with the second touch electrode and is electrically isolated from the second touch electrode. A dummy portion of the first conductive pattern is electrically connected to the third touch electrode and structurally separated from the main portion of the first conductive pattern.Type: ApplicationFiled: September 17, 2019Publication date: December 17, 2020Applicant: Au Optronics CorporationInventors: Hsun-Chen Chu, Pei-Ming Chen
-
Publication number: 20200225793Abstract: A touch display panel is provided, including a common electrode ring, a first and a second common electrode pattern, pixel structures, an edge common signal line, and common signal lines disposed on a substrate. The first and second common electrode patterns and the pixel structures are located in a region surrounded by the common electrode ring. The first common electrode pattern is spaced from the second common electrode pattern by a gap. The first and the second common electrode patterns respectively overlap some of the pixel structures. The edge common signal line is disposed on the substrate, traces along the gap, and extends toward the common electrode ring to be electrically connected to the common electrode ring. The first common electrode pattern overlaps and is electrically connected to one common signal line. The second common electrode pattern overlaps and is electrically connected to another common signal line.Type: ApplicationFiled: October 8, 2019Publication date: July 16, 2020Applicant: Au Optronics CorporationInventors: Te-Chun Huang, Wen-Yi Hsu, Zeng-De Chen, Pei-Ming Chen
-
Patent number: 10600812Abstract: A manufacturing method of an array substrate including following steps is provided. A plurality of scan lines are formed on a substrate having a pixel region and a fan-out region. A plurality of data lines are formed. A plurality of transistors are formed and respectively electrically connected to the corresponding scan lines and data lines. A plurality of common electrodes are formed. A plurality of pixel electrodes are formed and respectively electrically connected to the corresponding transistors. A plurality of first fan-out lines, second fan-out lines, and third fan-out lines are formed in the fan-out region. Each of the third fan-out lines includes a transparent conductive layer and an auxiliary conductive layer located on and contacting the transparent conductive layer. The third fan-out lines and the common electrodes are formed by the same photomask.Type: GrantFiled: January 15, 2019Date of Patent: March 24, 2020Assignee: Au Optronics CorporationInventors: Wen-Yi Hsu, Pei-Ming Chen, Maw-Song Chen
-
Publication number: 20190386032Abstract: A manufacturing method of an array substrate including following steps is provided. A plurality of scan lines are formed on a substrate having a pixel region and a fan-out region. A plurality of data lines are formed. A plurality of transistors are formed and respectively electrically connected to the corresponding scan lines and data lines. A plurality of common electrodes are formed. A plurality of pixel electrodes are formed and respectively electrically connected to the corresponding transistors. A plurality of first fan-out lines, second fan-out lines, and third fan-out lines are formed in the fan-out region. Each of the third fan-out lines includes a transparent conductive layer and an auxiliary conductive layer located on and contacting the transparent conductive layer. The third fan-out lines and the common electrodes are formed by the same photomask.Type: ApplicationFiled: January 15, 2019Publication date: December 19, 2019Applicant: Au Optronics CorporationInventors: Wen-Yi Hsu, Pei-Ming Chen, Maw-Song Chen
-
Publication number: 20170301701Abstract: An active device includes a poly-silicon semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer, a first through hole, an oxide semiconductor layer, a first electrode and a second electrode. The poly-silicon semiconductor layer includes a first doped region, a channel region and a second doped region. The gate electrode is disposed on the first insulating layer covering the poly-silicon semiconductor layer, and corresponds to the channel region. The gate electrode is covered by the second insulating layer, where the first and second insulating layers have a first through hole. The oxide semiconductor layer is disposed on the second insulating layer and corresponds to the gate electrode. The first and second electrodes are oppositely disposed on the oxide semiconductor layer. The oxide semiconductor layer is electrically connected to the second electrode, and to the second doped region via the first through hole.Type: ApplicationFiled: December 22, 2016Publication date: October 19, 2017Inventor: Pei-Ming CHEN
-
Patent number: 9793302Abstract: An active device includes a poly-silicon semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer, a first through hole, an oxide semiconductor layer, a first electrode and a second electrode. The poly-silicon semiconductor layer includes a first doped region, a channel region and a second doped region. The gate electrode is disposed on the first insulating layer covering the poly-silicon semiconductor layer, and corresponds to the channel region. The gate electrode is covered by the second insulating layer, where the first and second insulating layers have a first through hole. The oxide semiconductor layer is disposed on the second insulating layer and corresponds to the gate electrode. The first and second electrodes are oppositely disposed on the oxide semiconductor layer. The oxide semiconductor layer is electrically connected to the second electrode, and to the second doped region via the first through hole.Type: GrantFiled: December 22, 2016Date of Patent: October 17, 2017Assignee: AU OPTRONICS CORPORATIONInventor: Pei-Ming Chen
-
Patent number: 9698180Abstract: An integration method of fabricating optical sensor device and thin film transistor device includes the follow steps. A substrate is provided, and a gate electrode and a bottom electrode are formed on the substrate. A first insulating layer is formed on the gate electrode and the bottom electrode, and the first insulating layer at least partially exposes the bottom electrode. An optical sensing pattern is formed on the bottom electrode. A patterned transparent semiconductor layer is formed on the first insulating layer, wherein the patterned transparent semiconductor layer includes a first transparent semiconductor pattern covering the gate electrode, and a second transparent semiconductor pattern covering the optical sensing pattern. A source electrode and a drain electrode are formed on the first transparent semiconductor pattern.Type: GrantFiled: March 29, 2016Date of Patent: July 4, 2017Assignee: AU OPTRONICS CORP.Inventors: Shin-Shueh Chen, Pei-Ming Chen
-
Publication number: 20170069667Abstract: An integration method of fabricating optical sensor device and thin film transistor device includes the follow steps. A substrate is provided, and a gate electrode and a bottom electrode are formed on the substrate. A first insulating layer is formed on the gate electrode and the bottom electrode, and the first insulating layer at least partially exposes the bottom electrode. An optical sensing pattern is formed on the bottom electrode. A patterned transparent semiconductor layer is formed on the first insulating layer, wherein the patterned transparent semiconductor layer includes a first transparent semiconductor pattern covering the gate electrode, and a second transparent semiconductor pattern covering the optical sensing pattern. A source electrode and a drain electrode are formed on the first transparent semiconductor pattern.Type: ApplicationFiled: March 29, 2016Publication date: March 9, 2017Inventors: Shin-Shueh Chen, Pei-Ming Chen
-
Patent number: 9064749Abstract: An array substrate includes a substrate and a plurality of pixel structures. At least one pixel structure includes a gate electrode, a gate insulating layer, a source electrode and a drain electrode, a patterned semiconductor layer, a first passivation layer, and a transparent conductive pattern disposed in a pixel region of the substrate. The patterned semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern. The first semiconductor pattern substantially corresponds to the gate electrode and covers a portion of the source electrode and a portion of the drain electrode. The second semiconductor pattern covers a portion of the drain electrode. The first passivation layer is disposed on the patterned semiconductor layer and has a first opening exposing a portion of the second semiconductor pattern. The transparent conductive pattern is disposed on the first passivation layer and electrically connected to the second semiconductor pattern through the first opening.Type: GrantFiled: October 28, 2014Date of Patent: June 23, 2015Assignee: AU Optronics Corp.Inventors: Ming-Yao Chen, Pei-Ming Chen
-
Publication number: 20150048367Abstract: An array substrate includes a substrate and a plurality of pixel structures. At least one pixel structure includes a gate electrode, a gate insulating layer, a source electrode and a drain electrode, a patterned semiconductor layer, a first passivation layer, and a transparent conductive pattern disposed in a pixel region of the substrate. The patterned semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern. The first semiconductor pattern substantially corresponds to the gate electrode and covers a portion of the source electrode and a portion of the drain electrode. The second semiconductor pattern covers a portion of the drain electrode. The first passivation layer is disposed on the patterned semiconductor layer and has a first opening exposing a portion of the second semiconductor pattern. The transparent conductive pattern is disposed on the first passivation layer and electrically connected to the second semiconductor pattern through the first opening.Type: ApplicationFiled: October 28, 2014Publication date: February 19, 2015Inventors: Ming-Yao Chen, Pei-Ming Chen
-
Patent number: 8900900Abstract: A manufacturing method of an array substrate includes the following steps. A substrate having pixel region and a peripheral region is provided. A plurality of pixel structures are formed in the pixel region, wherein at least one of the pixel structures is formed by the following steps. A gate electrode, a gate insulating layer, and a source electrode and a drain electrode are formed. A patterned semiconductor layer including a first semiconductor pattern and a second semiconductor pattern is formed. The second semiconductor pattern covers a portion of the drain electrode. A first passivation layer is formed. The first passivation layer has a first opening exposing a portion of the second semiconductor pattern. A transparent conductive pattern is formed on the first passivation layer, and the transparent conductive pattern is electrically connected to the second semiconductor pattern through the first opening.Type: GrantFiled: February 21, 2013Date of Patent: December 2, 2014Assignee: AU Optronics Corp.Inventors: Ming-Yao Chen, Pei-Ming Chen
-
Publication number: 20140138714Abstract: A manufacturing method of an array substrate includes the following steps. A substrate having pixel region and a peripheral region is provided. A plurality of pixel structures are formed in the pixel region, wherein at least one of the pixel structures is formed by the following steps. A gate electrode, a gate insulating layer, and a source electrode and a drain electrode are formed. A patterned semiconductor layer including a first semiconductor pattern and a second semiconductor pattern is formed. The second semiconductor pattern covers a portion of the drain electrode. A first passivation layer is formed. The first passivation layer has a first opening exposing a portion of the second semiconductor pattern. A transparent conductive pattern is formed on the first passivation layer, and the transparent conductive pattern is electrically connected to the second semiconductor pattern through the first opening.Type: ApplicationFiled: February 21, 2013Publication date: May 22, 2014Applicant: AU OPTRONICS CORP.Inventors: Ming-Yao Chen, Pei-Ming Chen
-
Patent number: 8581256Abstract: A pixel structure and its fabrication method are provided. The pixel structure includes a channel layer, a first patterned metal layer, a first insulation layer, a second patterned metal layer, a second insulation layer, and a pixel electrode. The first patterned metal layer includes a data line, a source, and a drain. The first insulation layer has a first opening exposing the drain. The second patterned metal layer includes a scan line and a capacitor electrode. The capacitor electrode has at least one first portion overlapping the data line. The second insulation layer has a second opening communicating with the first opening to expose the drain. The pixel electrode is connected to the drain through the first opening and the second opening and at least overlaps the first portion of the capacitor electrode.Type: GrantFiled: March 26, 2012Date of Patent: November 12, 2013Assignee: Au Optronics CorporationInventors: Chang-Yu Huang, Pei-Ming Chen
-
Patent number: 8564584Abstract: An electrophoretic display with threshold voltage drift compensation functionality includes a gate driving circuit, a data driving circuit, a controller and a pixel array. The gate driving circuit provides plural gate signals according to a scan control signal. The data driving circuit provides plural data signals according to a data control signal. The controller is employed to provide the scan control signal and the data control signal. The pixel array is utilized for displaying images according to the gate signals and the data signals. Each of the gate signals includes a writing enable pulse for enabling write operations of the data signals during a writing period. And during a compensation period, each of the gate signals includes a compensation pulse for performing threshold voltage drift compensation operations on the data switches of the pixel array, and the data signals are set to hold a common voltage.Type: GrantFiled: May 6, 2010Date of Patent: October 22, 2013Assignee: AU Optronics Corp.Inventors: Chang-Yu Huang, Chuan-Sheng Wei, Pei-Ming Chen, Chun-Hsiun Chen, Wei-Ming Huang
-
Patent number: 8450157Abstract: A master having a substrate including displaying units and an ESD protection structure including an adjacent first region and a second region is provided. The displaying units have a predetermined-cutting region therebetween. Each displaying unit includes a peripheral circuit region and a display region having pixels.Type: GrantFiled: December 28, 2011Date of Patent: May 28, 2013Assignee: Au Optronics CorporationInventors: Pei-Ming Chen, Chih-Hung Shih