Abstract: A pixel structure and its fabrication method are provided. The pixel structure includes a channel layer, a first patterned metal layer, a first insulation layer, a second patterned metal layer, a second insulation layer, and a pixel electrode. The first patterned metal layer includes a data line, a source, and a drain. The first insulation layer has a first opening exposing the drain. The second patterned metal layer includes a scan line and a capacitor electrode. The capacitor electrode has at least one first portion overlapping the data line. The second insulation layer has a second opening communicating with the first opening to expose the drain. The pixel electrode is connected to the drain through the first opening and the second opening and at least overlaps the first portion of the capacitor electrode.

Abstract: A (liquid crystal display) LCD includes a pixel array and a gate driving circuit. The pixel array includes a plurality of first oxide thin film transistors, a first oxide thin film transistor of the first oxide thin film transistors with a shortest channel length having a first channel length. The gate driving circuit is coupled to the pixel array for driving the pixel array, and includes a plurality of second oxide thin film transistors. The second oxide thin film of the second oxide thin film transistors with a longest channel length has a second channel length. A ratio of the second channel length and the first channel length is greater than 1.5. By limiting the ratio of the second channel length and the first channel length, the aperture ratio of the display panel can be improved without deteriorating the operation stability of the LCD.

Abstract: A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.

Abstract: An electrophoresis display panel including an active device array substrate and an electrophoresis display film is provided. The active device array substrate includes a plurality of active devices and a shielding pattern. The electrophoresis display film is disposed on the active device array substrate. The electrophoresis display film includes a conductive layer, a dielectric layer and a plurality of electrophoresis display mediums. The dielectric layer is disposed on the conductive layer and has a plurality of micro-cups arranged in area array. The dielectric layer is between the conductive layer and the active device array substrate. Light passing through the dielectric layer is prevented from irradiating onto the active devices by the shielding pattern. In addition, the electrophoresis display mediums are filled within the micro-cups, respectively.

Abstract: A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.

Abstract: A master having a substrate including displaying units and an ESD protection structure including an adjacent first region and a second region is provided. The displaying units have a predetermined-cutting region therebetween. Each displaying unit includes a peripheral circuit region and a display region having pixels.

Abstract: A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other.

Abstract: A master having a substrate including displaying units and an ESD protection structure including an adjacent first region and a second region is provided. The displaying units have a predetermined-cutting region therebetween. Each displaying unit includes a peripheral circuit region and a display region having pixels.

Abstract: A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.

Abstract: An electrophoresis display panel including an active device array substrate and an electrophoresis display film is provided. The active device array substrate includes a plurality of active devices and a shielding pattern. The electrophoresis display film is disposed on the active device array substrate. The electrophoresis display film includes a conductive layer, a dielectric layer and a plurality of electrophoresis display mediums. The dielectric layer is disposed on the conductive layer and has a plurality of micro-cups arranged in area array. The dielectric layer is between the conductive layer and the active device array substrate. Light passing through the dielectric layer is prevented from irradiating onto the active devices by the shielding pattern. In addition, the electrophoresis display mediums are filled within the micro-cups, respectively.

Abstract: An electrophoresis display panel including an active device array substrate and an electrophoresis display film is provided. The active device array substrate includes a plurality of active devices and a shielding pattern. The electrophoresis display film is disposed on the active device array substrate. The electrophoresis display film includes a conductive layer, a dielectric layer and a plurality of electrophoresis display mediums. The dielectric layer is disposed on the conductive layer and has a plurality of micro-cups arranged in area array. The dielectric layer is between the conductive layer and the active device array substrate. Light passing through the dielectric layer is prevented from irradiating onto the active devices by the shielding pattern. In addition, the electrophoresis display mediums are filled within the micro-cups, respectively.

Abstract: An electrophoretic display with threshold voltage drift compensation functionality includes a gate driving circuit, a data driving circuit, a controller and a pixel array. The gate driving circuit provides plural gate signals according to a scan control signal. The data driving circuit provides plural data signals according to a data control signal. The controller is employed to provide the scan control signal and the data control signal. The pixel array is utilized for displaying images according to the gate signals and the data signals. Each of the gate signals includes a writing enable pulse for enabling write operations of the data signals during a writing period. And during a compensation period, each of the gate signals includes a compensation pulse for performing threshold voltage drift compensation operations on the data switches of the pixel array, and the data signals are set to hold a common voltage.

Abstract: An electrophoresis display panel including an active device array substrate and an electrophoresis display film is provided. The active device array substrate includes a plurality of active devices and a shielding pattern. The electrophoresis display film is disposed on the active device array substrate. The electrophoresis display film includes a conductive layer, a dielectric layer and a plurality of electrophoresis display mediums. The dielectric layer is disposed on the conductive layer and has a plurality of micro-cups arranged in area array. The dielectric layer is between the conductive layer and the active device array substrate. Light passing through the dielectric layer is prevented from irradiating onto the active devices by the shielding pattern. In addition, the electrophoresis display mediums are filled within the micro-cups, respectively.

Abstract: A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other.

Abstract: An active TFT circuit structure with current scaling function is disclosed, which includes a current source, a data line, a scan line, a direct current voltage source, capacitors and four transistors, wherein the capacitors form a cascade structure. During the ON-state, the two of the transistors are turn-on based on the voltage provided by the scan line, so that the data current provided by the current source flows through the data line-and the transistor which is one of the opened transistors, thereby arriving an emitting light element and the transistor connected to the emitting light element. When the pixel circuit changes from ON- to OFF-state, the voltage of the node between the storage capacitors reduces due to the feed-through effect of one of storage capacitor, thereby reducing the driving current of the emitting light element. Therefore, it can be achieved the current scaling function.

Abstract: A master having a substrate including displaying units and an ESD protection structure including an adjacent first region and a second region is provided. The displaying units have a predetermined-cutting region therebetween. Each displaying unit includes a peripheral circuit region and a display region having pixels.

Abstract: An OLED display, an OLED panel and a driving device are disclosed. Wherein, the OLED display includes the OLED and the driving device. The OLED panel has a plurality of display pixels, every display pixel includes a plurality of sub-pixels, and each of the sub-pixels respectively corresponds to a different color. The driving device includes a plurality of current mirrors for correspondingly receiving one of a plurality of data currents and for generating driving currents sent to the corresponding sub-pixels, respectively. Each the current mirror includes a plurality of transistors and generates a different driving current to drive the corresponding sub-pixels according to the ratios between the channel widths and channel lengths of the transistors in the current mirror.

Abstract: An active TFT circuit structure with current scaling function is disclosed, which includes a current source, a data line, a scan line, a direct current voltage source, capacitors and four transistors, wherein the capacitors form a cascade structure. During the ON-state, the two of the transistors are turn-on based on the voltage provided by the scan line, so that the data current provided by the current source flows the data line and the transistor which is one of the opened transistors, thereby arriving an emitting light element and the transistor connected to the emitting light element. When the pixel circuit changes from ON- to OFF-state, the voltage of the node between the storage capacitors reduces due to the feed-through effect of one of storage capacitor, thereby reducing the driving current of the emitting light element. Therefore, it can be achieved the current scaling function.

Abstract: An embedded controller and a computer system with the same are provided. The embedded controller includes a control unit and a firmware. The embedded controller also has a memory device embedded therein or connected thereto. By a synchronal software tool or a driver, the personal information data stored in the personal information software is synchronized with the data stored in the memory device of the embedded controller. When the computer is shut down or is in a sleeping mode, the embedded controller takes over handling the events scheduled in the personal information software. Whenever any scheduled event occurs, the embedded controller notifies the user by a sound or a displayed message. The embedded controller can also synchronize the data stored in the memory device with a hand-held device connected to the computer system when the computer is shut down or in a sleeping mode.