Patents by Inventor Pei-Yi Liu
Pei-Yi Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170176849Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.Type: ApplicationFiled: March 2, 2017Publication date: June 22, 2017Inventors: JYUH-FUH LIN, CHENG-HUNG CHEN, PEI-YI LIU, WEN-CHUAN WANG, SHY-JAY LIN, BURN JENG LIN
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Publication number: 20170168197Abstract: The invention provides a material for contact lenses, including a first siloxane macromer shown as formula (I): in formula (I), R1, R2 and R3 are C1-C4 alkyl groups, R4 is C1-C6 alkyl group, R5 is C1-C4 alkylene group, R6 is —OR7O— or —NH—, R7 and R8 are C1-C4 alkylene groups and m is an integer of about 1-2, n is an integer of about 4-80; a second siloxane macromer shown as formula (II): in formula (II), R9, R10 and R11 are C1-C4, alkyl groups, R12, R13 and R15 are C1-C3 alkylene group. R14 is a residue obtained by removing NCO group from an aliphatic or aromatic diisocyanate, and o is an integer of about 4-80, p is an integer of about 0-1; q is an integer of about 1-20; at least one hydrophilic monomer and an initiator.Type: ApplicationFiled: February 24, 2017Publication date: June 15, 2017Inventors: Fan-Dan JAN, Pei-Yi LIU
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Patent number: 9678434Abstract: Lithography methods disclosed herein accommodate shrinking pattern dimensions. An exemplary method includes receiving a pattern to be transferred to a workpiece by a pattern generator. The pattern generator is divided into a first segment set and a second segment set based on the pattern, such that a collective exposure dose from the first segment set and the second segment set satisfies an exposure dose specified by the pattern. The first segment set is offset from the second segment set in a first direction, and segments in the first segment set and segments in the second segment set are offset from each other in a second direction different than the first direction. The method further includes exposing the workpiece according to the first segment set and the second segment set.Type: GrantFiled: December 22, 2016Date of Patent: June 13, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chuan Wang, Burn Jeng Lin, Jaw-Jung Shin, Pei-Yi Liu, Shy-Jay Lin
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Patent number: 9658538Abstract: A technique for converting design shapes into pixel values is provided. The technique may be used to control a direct-write or other lithographic process performed on a workpiece. In an exemplary embodiment, the method includes receiving, at a computing system, a design database specifying a feature having more than four vertices. The computing system also receives a pixel grid. A set of rectangles corresponding to the feature is determined, and the computing system determines an area of a pixel of the pixel grid overlapped by the feature based on the set of rectangles. In some such embodiments, a lithographic exposure intensity is determined for the pixel based on the area overlapped by the feature, and the lithographic exposure intensity is provided for patterning of a workpiece.Type: GrantFiled: December 19, 2014Date of Patent: May 23, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Yi Liu, Cheng-Chi Wu, Cheng-Hung Chen, Jyuh-Fuh Lin, Wen-Chuan Wang, Shy-Jay Lin
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Publication number: 20170102624Abstract: Lithography methods disclosed herein accommodate shrinking pattern dimensions. An exemplary method includes receiving a pattern to be transferred to a workpiece by a pattern generator. The pattern generator is divided into a first segment set and a second segment set based on the pattern, such that a collective exposure dose from the first segment set and the second segment set satisfies an exposure dose specified by the pattern. The first segment set is offset from the second segment set in a first direction, and segments in the first segment set and segments in the second segment set are offset from each other in a second direction different than the first direction. The method further includes exposing the workpiece according to the first segment set and the second segment set.Type: ApplicationFiled: December 22, 2016Publication date: April 13, 2017Inventors: Wen-Chuan Wang, Burn Jeng Lin, Jaw-Jung Shin, Pei-Yi Liu, Shy-Jay Lin
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Patent number: 9594862Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize an uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for non-printable dummy features and adding the non-printable dummy features in the IC design layout.Type: GrantFiled: June 20, 2014Date of Patent: March 14, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyuh-Fuh Lin, Cheng-Hung Chen, Pei-Yi Liu, Wen-Chuan Wang, Shy-Jay Lin, Burn Jeng Lin
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Patent number: 9552964Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.Type: GrantFiled: September 11, 2014Date of Patent: January 24, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyuh-Fuh Lin, Cheng-Hung Chen, Pei-Yi Liu, Wen-Chuan Wang, Shy-Jay Lin, Burn Jeng Lin
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Patent number: 9529271Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.Type: GrantFiled: May 2, 2016Date of Patent: December 27, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chuan Wang, Burn Jeng Lin, Jaw-Jung Shin, Pei-Yi Liu, Shy-Jay Lin
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Publication number: 20160370503Abstract: The invention provides a material for contact lenses, including a first siloxane macromer shown as formula (I): in formula (I), R1, R2 and R3 are C1-C4 alkyl groups, R4 is C1-C6 alkyl group, R5 is C1-C4 alkylene group, R6 is —OR7O— or —NH—, R7 and R8 are C1-C4 alkylene groups and m is an integer of about 1-2, n is an integer of about 4-80; a second siloxane macromer shown as formula (II): in formula (II), R9, R10 and R11 are C1-C4 alkyl groups, R12, R13 and R15 are C1-C3 alkylene group, R14 is a residue obtained by removing NCO group from an aliphatic or aromatic diisocyanate, and o is an integer of about 4-80, p is an integer of about 0-1; q is an integer of about 1-20; at least one hydrophilic monomer and an initiator.Type: ApplicationFiled: November 4, 2015Publication date: December 22, 2016Inventors: Fan-Dan JAN, Pei-Yi LIU
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Patent number: 9436788Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a plurality of main features; choosing isolation distances to the IC design layout; oversizing the main features according to each of the isolation distances; generating a space block layer for the each of the isolation distances by a Boolean operation according to oversized main features; choosing an optimized space block layer and an optimized block dummy density ratio of the IC design layout according to pattern density variation; generating dummy features in the optimized space block layer according to the optimized block dummy density ratio; and forming a tape-out data of the IC design layout including the main features and the dummy features, for IC fabrication.Type: GrantFiled: April 15, 2014Date of Patent: September 6, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyuh-Fuh Lin, Pei-Yi Liu, Cheng-Hung Chen, Wen-Chuan Wang, Shy-Jay Lin, Burn Jeng Lin
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Patent number: 9436787Abstract: The present disclosure provides a method that includes receiving an IC design layout having main features and generating a plurality of space block layers to the IC design layout. The method also includes calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout and calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space block layers according to the main pattern density and the dummy pattern density. The method further includes choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR and generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio. Additionally, the method includes forming a tape-out data of the modified IC design layout for IC fabrication.Type: GrantFiled: April 14, 2014Date of Patent: September 6, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyuh-Fuh Lin, Pei-Yi Liu, Cheng-Hung Chen, Wen-Chuan Wang, Shy-Jay Lin, Burn Jeng Lin
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Publication number: 20160246912Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size Si to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.Type: ApplicationFiled: May 2, 2016Publication date: August 25, 2016Inventors: WEN-CHUAN WANG, BURN JENG LIN, JAW-JUNG SHIN, PEI-YI LIU, SHY-JAY LIN
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Publication number: 20160180005Abstract: A technique for converting design shapes into pixel values is provided. The technique may be used to control a direct-write or other lithographic process performed on a workpiece. In an exemplary embodiment, the method includes receiving, at a computing system, a design database specifying a feature having more than four vertices. The computing system also receives a pixel grid. A set of rectangles corresponding to the feature is determined, and the computing system determines an area of a pixel of the pixel grid overlapped by the feature based on the set of rectangles. In some such embodiments, a lithographic exposure intensity is determined for the pixel based on the area overlapped by the feature, and the lithographic exposure intensity is provided for patterning of a workpiece.Type: ApplicationFiled: December 19, 2014Publication date: June 23, 2016Inventors: Pei-Yi Liu, Cheng-Chi Wu, Cheng-Hung Chen, Jyuh-Fuh Lin, Wen-Chuan Wang, Shy-Jay Lin
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Patent number: 9329488Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.Type: GrantFiled: October 30, 2015Date of Patent: May 3, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
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Publication number: 20160055291Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.Type: ApplicationFiled: October 30, 2015Publication date: February 25, 2016Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
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Publication number: 20150370942Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize an uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for non-printable dummy features and adding the non-printable dummy features in the IC design layout.Type: ApplicationFiled: June 20, 2014Publication date: December 24, 2015Inventors: Jyuh-Fuh Lin, Cheng-Hung Chen, Pei-Yi Liu, Wen-Chuan Wang, Shy-Jay Lin, Burn Jeng Lin
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Publication number: 20150338681Abstract: A method for manufacturing a colored contact lens which comprises the steps of: (a) forming a contact lens by polymerizing a polymerizable lens forming material in a mold, wherein the lens forming material includes at least one reactive group; (b) contacting at least a part of the contact lens with a dye solution for a period of time sufficient to form a colored layer within the contact lens, wherein the dye solution includes at least one dye of ?-sulphatoethyl sulphone substituted with a sulfonate group; (c) immersing the contact lens with colored layer in a fixing solution; and (d) washing the contact lens; wherein the colored layer is covalently attached to the contact lens.Type: ApplicationFiled: March 3, 2015Publication date: November 26, 2015Inventors: Pei-Yi LIU, Hsia-Hao CHANG, Yu-Syun SHIN, Mei-Yun CHANG
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Patent number: 9176389Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.Type: GrantFiled: August 28, 2014Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manfacturing Company, Ltd.Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
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Publication number: 20150294056Abstract: The present disclosure provides an IC method that includes receiving an IC design layout having main features; generating a plurality of space block layers to the IC design layout, each of the space block layers being associated with an isolation distance and a plurality of space blocks; calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout; calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space layers according to the main pattern density and the dummy pattern density; choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR; generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio; and forming a tape-out data of the modified IC design layout for IC fabrication.Type: ApplicationFiled: April 14, 2014Publication date: October 15, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyuh-Fuh Lin, Pei-Yi Liu, Cheng-Hung Chen, Wen-Chuan Wang, Shy-Jay Lin, Burn Jeng Lin
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Publication number: 20150294057Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a plurality of main features; choosing isolation distances to the IC design layout; oversizing the main features according to each of the isolation distances; generating a space block layer for the each of the isolation distances by a Boolean operation according to oversized main features; choosing an optimized space block layer and an optimized block dummy density ratio of the IC design layout according to pattern density variation; generating dummy features in the optimized space block layer according to the optimized block dummy density ratio; and forming a tape-out data of the IC design layout including the main features and the dummy features, for IC fabrication.Type: ApplicationFiled: April 15, 2014Publication date: October 15, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyuh-Fuh Lin, Pei-Yi Liu, Cheng-Hung Chen, Wen-Chuan Wang, Shy-Jay Lin, Burn Jeng Lin