Patents by Inventor Pei-Yi Liu
Pei-Yi Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9134627Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes forming a first structure in a first layer by a first exposure and determining placement information of the first structure. The method further includes forming a second structure in a second layer overlying the first layer by a second exposure and determining placement information of the second structure. The method further includes forming a third structure including first and second substructures in a third layer overlying the second layer by a third exposure. Forming the third structure includes independently aligning the first substructure to the first structure and independently aligning the second substructure to the second structure.Type: GrantFiled: December 16, 2011Date of Patent: September 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
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Patent number: 8984452Abstract: A method of quantifying a lithographic proximity effect and determining a lithographic exposure dosage is disclosed. In an exemplary embodiment, the method for determining an exposure dosage comprises receiving a design database including a plurality of features intended to be formed on a workpiece. A target region of the design database is defined such that the target region includes a target feature. A region of the design database proximate to the target region is also defined. An approximation for the region is determined, where the approximation represents an exposed area within the region. A proximity effect of the region upon the target feature is determined based on the approximation for the region. A total proximity effect for the target feature is determined based on the determined proximity effect of the region upon the target feature.Type: GrantFiled: August 13, 2013Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chen, Shy-Jay Lin, Jaw-Jung Shin, Wen-Chuan Wang, Pei-Yi Liu, Burn Jeng Lin
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Patent number: 8972908Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a feature; fracturing the feature into a plurality of polygons that includes a first polygon; assigning target points to edges of the first polygon; calculating corrected exposure doses to the first polygon, wherein each of the correct exposure doses is determined based on a respective one of the target points by simulation; determining a polygon exposure dose to the first polygon based on the corrected exposure doses; and preparing a tape-out data for lithography patterning, wherein the tape-out data defines the plurality of polygons and a plurality of polygon exposure doses paired with the plurality of polygons.Type: GrantFiled: July 30, 2013Date of Patent: March 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chen, Jaw-Jung Shin, Shy-Jay Lin, Wen-Chuan Wang, Pei-Yi Liu, Burn Jeng Lin
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Publication number: 20150052489Abstract: A method of quantifying a lithographic proximity effect and determining a lithographic exposure dosage is disclosed. In an exemplary embodiment, the method for determining an exposure dosage comprises receiving a design database including a plurality of features intended to be formed on a workpiece. A target region of the design database is defined such that the target region includes a target feature. A region of the design database proximate to the target region is also defined. An approximation for the region is determined, where the approximation represents an exposed area within the region. A proximity effect of the region upon the target feature is determined based on the approximation for the region. A total proximity effect for the target feature is determined based on the determined proximity effect of the region upon the target feature.Type: ApplicationFiled: August 13, 2013Publication date: February 19, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chen, Shy-Jay Lin, Jaw-Jung Shin, Wen-Chuan Wang, Pei-Yi Liu, Burn Jeng Lin
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Publication number: 20150040079Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a feature; fracturing the feature into a plurality of polygons that includes a first polygon; assigning target points to edges of the first polygon; calculating corrected exposure doses to the first polygon, wherein each of the correct exposure doses is determined based on a respective one of the target points by simulation; determining a polygon exposure dose to the first polygon based on the corrected exposure doses; and preparing a tape-out data for lithography patterning, wherein the tape-out data defines the plurality of polygons and a plurality of polygon exposure doses paired with the plurality of polygons.Type: ApplicationFiled: July 30, 2013Publication date: February 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chen, Jaw-Jung Shin, Shy-Jay Lin, Wen-Chuan Wang, Pei-Yi Liu, Burn Jeng Lin
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Publication number: 20140368806Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.Type: ApplicationFiled: August 28, 2014Publication date: December 18, 2014Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
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Patent number: 8828632Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.Type: GrantFiled: September 4, 2013Date of Patent: September 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
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Patent number: 8822107Abstract: The present disclosure provide one embodiment of a method of a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel area S1 to generate a data grid having a second pixel area S2 that is equal to n2*S1, wherein the pattern generator includes a multi-segment structure having multiple grid segments, wherein the grid segments includes a first set of grid segments and a second set of grid segments, each of the first set of grid segments being configured to have an offset in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each of the second set of grid segments is controlled to have a time delay.Type: GrantFiled: January 30, 2013Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
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Patent number: 8822106Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.Type: GrantFiled: December 20, 2012Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
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Publication number: 20140004468Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.Type: ApplicationFiled: September 4, 2013Publication date: January 2, 2014Inventors: Wen-Chuan Wang, Shy-Jay Lin, Chih-Hsun Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
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Patent number: 8584057Abstract: A method of data preparation in lithography processes is described. The method includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, converting the IC layout design GDS grid to a first exposure grid, applying a non-directional dither technique to the first exposure, coincident with applying dithering to the first expose grid, applying a grid shift to the first exposure grid to generate a grid-shifted exposure grid and applying a dither to the grid-shifted exposure grid, and adding the first exposure grid (after receiving dithering) to the grid-shifted exposure grid (after receiving dithering) to generate a second exposure grid.Type: GrantFiled: March 1, 2012Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Copmany, Ltd.Inventors: Pei-Yi Liu, Shy-Jay Lin, Wen-Chuan Wang, Jaw-Jung Shin, Burn Jeng Lin
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Publication number: 20130273475Abstract: The present disclosure provide one embodiment of a method of a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel area S1 to generate a data grid having a second pixel area S2 that is equal to n2*S1, wherein the pattern generator includes a multi-segment structure having multiple grid segments, wherein the grid segments includes a first set of grid segments and a second set of grid segments, each of the first set of grid segments being configured to have an offset in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each of the second set of grid segments is controlled to have a time delay.Type: ApplicationFiled: January 30, 2013Publication date: October 17, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
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Publication number: 20130273474Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.Type: ApplicationFiled: December 20, 2012Publication date: October 17, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
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Patent number: 8530121Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.Type: GrantFiled: February 8, 2012Date of Patent: September 10, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
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Publication number: 20130232455Abstract: The present disclosure involves a method of data preparation in lithography processes. The method of data preparation includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, and converting the IC layout design GDS grid to a second exposure grid by applying an error diffusion and a grid shift technique to a sub-pixel exposure grid.Type: ApplicationFiled: March 1, 2012Publication date: September 5, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Yi Liu, Shy-Jay Lin, Wen-Chuan Wang, Jaw-Jung Shin, Burn Jeng Lin
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Publication number: 20130232453Abstract: A method of data preparation in lithography processes is described. The method includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, converting the IC layout design GDS grid to a first exposure grid, applying a non-directional dither technique to the first exposure, coincident with applying dithering to the first expose grid, applying a grid shift to the first exposure grid to generate a grid-shifted exposure grid and applying a dither to the grid-shifted exposure grid, and adding the first exposure grid (after receiving dithering) to the grid-shifted exposure grid (after receiving dithering) to generate a second exposure grid.Type: ApplicationFiled: March 1, 2012Publication date: September 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Yi Liu, Shy-Jay Lin, Wen-Chuan Wang, Jaw-Jung Shin, Burn Jeng Lin
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Patent number: 8510687Abstract: The present disclosure involves a method of data preparation in lithography processes. The method of data preparation includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, and converting the IC layout design GDS grid to a second exposure grid by applying an error diffusion and a grid shift technique to a sub-pixel exposure grid.Type: GrantFiled: March 1, 2012Date of Patent: August 13, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Yi Liu, Shy-Jay Lin, Wen-Chuan Wang, Jaw-Jung Shin, Burn Jeng Lin
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Publication number: 20130203001Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.Type: ApplicationFiled: February 8, 2012Publication date: August 8, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
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Publication number: 20130157389Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes forming a first structure in a first layer by a first exposure and determining placement information of the first structure. The method further includes forming a second structure in a second layer overlying the first layer by a second exposure and determining placement information of the second structure. The method further includes forming a third structure including first and second substructures in a third layer overlying the second layer by a third exposure.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin