Abstract: A method of decorating a semiconductor substrate with an etchant solution is provided for revealing defects, such as microscratches, resulting from an oxide chemical-mechanical planarization (CMP) polishing. An oxide layer is provided over the substrate made from, for example, tetraethylorthosilicate (TEOS). The oxide layer is polished by a CMP process which tends to leave behind microscratches and other defects that can cause conductivity problems on the wafer. To reveal the microscratches, the wafer is decorated or submerged in an etchant, such as an HF etchant, for a period of time. Following the decorating, the wafer is rinsed, dried and inspected. The method improves the ability to identify and optimize steps in a semiconductor fabrication process that cause semiconductor defects.

Abstract: A method and semiconductor wafer is provided for measurement and recordation of hydrophilic elements in semiconductor insulators by depositing a moisture barrier layer over a previously deposited insulating layer of a semiconductor wafer. The semiconductor wafers become pilot or calibration wafers which may be placed immediately in an infrared radiation instrument to allow measurement of the concentration of hydrophilic elements in the insulating layer or stored for recordation purposes and measured later.

Abstract: A method of manufacturing semiconductor wafers wherein a metal layer is formed on a surface of a layer of interlayer dielectric on a partially completed semiconductor wafer and if it is determined that the metal layer is faulty, the faulty metal layer is removed, the surface of the layer of interlayer dielectric is lowered below the tops of metal plugs formed in the layer of interlayer dielectric, the tops of the metal plugs are planarized to the surface of the layer of interlayer dielectric and the metal layer is reformed on the surface of the interlayer dielectric. If the metal layer is determined to be good, the metal layer is etched. If the metal etch is faulty, the metal layer is removed, the layer of interlayer dielectric is reduced to below the tops of plugs formed in the layer of interlayer dielectric, the tops of the metal plugs are planarized down to the surface of the layer of interlayer dielectric and the layer of metal is reformed.