Abstract: A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.

Abstract: A system and method are provided for efficiently processing data with a cache in a computer system. The computer system has a processor, a cache and a system memory. The processor issues a data request for streaming data. The streaming data has one or more small data portions. The system memory is in communication with the processor. The system memory has a specific area for storing the streaming data. The cache is coupled to the processor. The cache has a predefined area locked for the streaming data. A cache controller is coupled to the cache and is in communication with both the processor and the system memory to transmit at least one small data portion of the streaming data from the specific area of the system memory to the predefined area of the cache when the one small data portion is not found in the predefined area of the cache.

Abstract: The present invention provides for determining an MRU or LRU way of a partitioned cache. The partitioned cache has a plurality of ways. There are a plurality of partitions, each partition comprising at least one way. An updater is employable to update a logic table as a function of an access of a way. Partition comparison logic is employable to determine whether two ways are members of the same partition, and to allow the comparison of the ways correlating to a first matrix indices and a second matrix indices. An intersection generator is employable to create an intersection box of the memory table as a function of a first and second matrix indices. Access order logic is employable to combine the output of the intersection generator, thereby determining which way is the most or least recently used way.

Abstract: A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.

Abstract: The present invention provides a data access ring. The data access ring has a plurality of attached processor units (APUs) and a local store associated with each APU. The data access ring has a data command ring, coupled to the plurality of APUs. The data command ring is employable to carry indicia of a selection of one of the plurality of APUs to the APUs. The data access ring also has a data address ring, coupled to the plurality of APUs. The data address ring is further employable to carry indicia of a memory location to the selected APU a predetermined number of clock cycles after the data command ring carries the indicia of the selection of one of the plurality of APUs. The data access ring also has a data transfer ring, coupled to the plurality of APUs. The data transfer ring is employable to transfer data to or from the memory location associated with the APU a predetermined number of clock cycles after the data address ring carries the indicia of the memory location to the selected APU.

Abstract: Disclosed is an electronic chip containing a plurality of electronic circuit partitions, distributed over the area of the chip, each including a processor core and a clock phase domain different from cores in other partitions of the chip. A source of same frequency, but different phase clock signals representing different clock domains, provides different phase signals to adjacent partitions for the purpose of reducing instantaneous magnitude switching currents. Intra-chip communication circuitry distributes control and data signals between partitions.

Abstract: A cache memory having a mechanism for managing cache lines replacement is disclosed. The cache memory comprises multiple cache lines partitioned into a first group and a second group. The number of cache lines in the second group is preferably larger than the number of cache lines in the first group. A replacement logic block selectively chooses a cache line from one of the two groups of cache lines for replacement during an allocation cycle.

Abstract: A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky bits. The execution unit is suitable for executing a set of computer instructions. The temporary result buffer is configured to receive, from the execution unit, register bit modification information provided by the instructions. The temporary result buffer is suitable for storing the modification information in set/clear pairs of bits corresponding to respective register bits of the register. The commit function circuit is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed. The commit function circuit is suitable for generating an updated bit in response to receiving the set/clear pairs of bits. The updated bit is then committed to the corresponding register bit of the register.

Abstract: A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated.

Abstract: An interleaved data cache array which is divided into two subarrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address (ECAM) for the selected block of data, a second content addressable field contains a real address (RCAM) for the selected block of data and a data status field. Separate effective address ports (EA) and a real address port (RA) permit parallel access to the cache without conflict in separate subarrays and a subarray arbitration logic circuit is provided for attempted simultaneous access of a single subarray by both the effective address port (EA) and the real address port (RA). A normal word line is provided and activated by either the effective address port or the real address port through the subarray arbitration.

Abstract: A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated.

Abstract: A cache memory having a selectable cache-line replacement scheme is described. In accordance with a preferred embodiment of the present invention, the cache memory has a number of cache lines, a number of token registers, a token, and a selection circuit. The token registers are connected to each other in a ring configuration. There is an equal number of token registers and cache lines, and each of the token registers is associated with one of the cache lines. The token is utilized to indicate one of the cache lines as a candidate for replacement by the associated token register in which the token settles. The selection circuit is associated with all of the token registers. This selection circuit provides at least two methods of controlling the movement of the token within the ring of the token registers, to be selectable during runtime. Each method of token movement represents a cache-line replacement scheme.

Abstract: A cache sub-array arbitration circuit for receiving a plurality of address operands from a pending line of processor instructions in order to pre-fetch data needed in any memory access request in the pending instructions. The sub-array arbitration circuit compares at least two addresses corresponding to memory locations in the cache, and determines in which sub-arrays the memory locations reside. If the two memory locations reside in the same sub-array, the arbitration circuit sends the higher priority address to the sub-array. If a received address operand is the real address of a cache miss, the arbitration circuit sends the cache miss address to the sub-array before other pre-fetch memory access request.

Abstract: An interleaved data cache array which is divided into two sub arrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a first content addressable field containing a portion of an effective address for the selected block of data, a second content addressable field contains a portion of the real address for the selected block of data and a data status field. By utilizing two separate content addresssable fields for the effective address and real address offset and alias problems may be efficiently resolved. A virtual address aliasing condition is identified by searching each cache line for a match between a portion of a desired effective address and the content of the first content addressable field.

Abstract: An interleaved data cache array which is divided into two subarrays. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address for the selected block of data, a second content addressable field contains a portion of the real address for the selected block of data and a data status field. By utilizing two separate content addressable fields for the effective address and real address offset and alias problems may be efficiently resolved. The data cache is preferably arranged as an eight way set-associative cache wherein each congruence class includes up to eight entries having identical low order address bits.

Abstract: A cache memory having a mechanism for managing offset and aliasing conditions is disclosed. In accordance with a preferred embodiment of the invention, the cache memory comprises a first directory circuit, a second directory circuit, a multiple number of most recently used bits, and a multiple number of set/reset circuits. The first directory circuit, having multiple caches lines, is utilized to receive partial effective addresses. The second directory circuit is utilized to receive an output from the first directory circuit. A most recently used bit is associated with each cache line within the first directory circuit. The set/reset circuit, coupled to each of the most recently used bits, is utilized to set one of the most recently used bits to a first state while concurrently resetting the rest of the most recently used bits to a second state within a single cycle during an occurrence of an offset or aliasing conditions such that offset or aliasing conditions can be more efficiently managed.

Abstract: A method and system of implementing a cache coherency mechanism for supporting a non-inclusive cache memory hierarchy within a data processing system is disclosed. In accordance with the method and system of the invention, the memory hierarchy includes a primary cache memory, a secondary cache memory, and a main memory. The primary cache memory and the secondary cache memory are non-inclusive. Further, a first state bit and a second state bit are provided within the primary cache, in association with each cache line of the primary cache. As a preferred embodiment, the first state bit is set only if a corresponding cache line in the primary cache memory has been modified under a write-through mode, while the second state bit is set only if a corresponding cache line also exists in the secondary cache memory. As such, the cache coherency between the primary cache memory and the secondary cache memory can be maintained by utilizing the first state bit and the second state bit in the primary cache memory.

Abstract: An interleaved cache memory having a single-cycle multi-access capability is disclosed. The interleaved cache memory comprises multiple subarrays of memory cells, an arbitration logic circuit for receiving multiple input addresses to those subarrays, and an address input circuit for applying the multiple input addresses to these subarrays. Each of these subarrays includes an even data section and an odd data section and three content-addressable memories to receive the multiple input addresses for comparison with tags stored in these three content-addressable memories. The first one of the three content-addressable memories is associated with the even data section and the second one of the three content-addressable memories is associated with the odd data section. The arbitration logic circuit is then utilized to select one of the multiple input addresses to proceed if more than one input address attempts to access the same data section of the same subarray.

Abstract: A cache memory for a computer uses content-addressable tag-compare arrays (CAM) to determine if a match occurs. The cache memory is partitioned in four subarrays, i.e., interleaved, providing a wide cache line (word lines) but shallow depth (bit lines). The cache can be accessed by multiple addresses, producing multiple data outputs in a given cycle. Two effective addresses and one real address are applied at one time, and if addresses are matched in different subarrays, or two on the same line in a single subarray, then multiple access is permitted. The two content-addressable memories, or CAMs, are used to select a cache line, and in parallel with this, arbitration logic in each subarray selects a word line (cache line).

Abstract: A compare circuit for a content-addressable memory within a computer system is disclosed. In accordance with a preferred embodiment of the present invention, a compare circuit for a content-addressable memory comprises a pair of storage node lines, a pair of compare lines, and two sets of transistors. The pair of storage node lines are complementary to each other and are connected to a memory cell of the content-addressable memory for determining a state of the memory cell. In a like manner, the pair of compare lines are also complementary to each other. The first set of transistors are four transistors connected in series to be enabled by a logical one from one of the storage node lines for allowing a signal from one of the compare lines to propagate to an output. The second set of transistors are also four transistors connected in series to be enabled by a logical zero from the same storage node line for allowing a signal from the other compare line to propagate to the output.