Patents by Inventor Peijie Feng

Peijie Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210320197
    Abstract: A multi-gate HEMT includes at least two gates, with at least one recessed the same depth or at a deeper depth in a barrier layer than at least one other gate. Recessing a gate decreases the thickness of the barrier layer beneath the gate, reducing a density of high mobility carriers in a two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer and a buffer layer below the recessed gate. The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Inventors: Chenjie Tang, Ye Lu, Peijie Feng, Junjing Bao
  • Publication number: 20210305155
    Abstract: An integrated circuit (IC) is described. The IC includes a substrate having an active device having an active region. The IC also includes a middle-of-line (MOL) interconnect layer having a contact merge (CM) layer on a trench contact coupled to the active region of the active device. The IC further includes back-end-of-line (BEOL) interconnect layers on the MOL interconnect layer. The IC also includes a metal resistor in a via zero interconnect layer between a first BEOL interconnect and the MOL interconnect layer. The metal resistor is coupled to the active region through a first via zero on the CM layer, a second via zero on the metal resistor, and the first BEOL interconnect on the first via zero and the second via zero.
    Type: Application
    Filed: March 30, 2020
    Publication date: September 30, 2021
    Inventors: Junjing BAO, Giridhar NALLAPATI, Peijie FENG
  • Publication number: 20210233909
    Abstract: Certain aspects of the present disclosure relate to a gate-all-around (GAA) semiconductor device. One example GAA semiconductor device includes a plurality of nanosheet stack structures disposed vertically above a horizontal plane of a substrate, wherein: each nanosheet stack structure of the plurality of nanosheet stack structures comprises one or more nanosheets; the one or more nanosheets of a first nanosheet stack structure of the plurality of nanosheet stack structures comprise a first semiconductor material; and the one or more nanosheets of a second nanosheet stack structure of the plurality of nanosheet stack structures comprise a second semiconductor material different from the first semiconductor material.
    Type: Application
    Filed: January 24, 2020
    Publication date: July 29, 2021
    Inventors: Junjing BAO, Ye LU, Peijie FENG, Chenjie TANG, Xiaochun ZHU
  • Publication number: 20210233911
    Abstract: Certain aspects of the present disclosure generally relate to a gate-all-around (GAA) semiconductor device. The GAA semiconductor device generally includes a substrate, a first nanosheet stack structure, a second nanosheet stack structure, the first and second nanosheet stack structures being disposed above a horizontal plane of the substrate and each comprising one or more nanosheet structures, and a dielectric structure disposed between the first nanosheet stack structure and the second nanosheet stack structure.
    Type: Application
    Filed: January 28, 2020
    Publication date: July 29, 2021
    Inventors: Peijie FENG, Ye LU, Junjing BAO, Chenjie TANG
  • Publication number: 20210057410
    Abstract: An integrated device that includes a substrate, a first transistor, and a second transistor. The second transistor is configured to be coupled to the first transistor. The first transistor is configured to operate as a N-type channel metal oxide semiconductor transistor (NMOS) transistor. The first transistor includes a dielectric layer disposed over the substrate; a first source disposed over the dielectric layer; a first drain disposed over the dielectric layer; a first plurality of channels coupled to the first source and the first drain; and a first gate surrounding the plurality of channels. The second transistor is configured to operate as a P-type channel metal oxide semiconductor transistor (PMOS). The second transistor includes the dielectric layer; a second source disposed over the dielectric layer; a second drain disposed over the dielectric layer; a second plurality of channels coupled to the second source and the second drain; and a second gate.
    Type: Application
    Filed: March 12, 2020
    Publication date: February 25, 2021
    Inventors: Stanley Seungchul SONG, Hyunwoo PARK, Peijie FENG
  • Publication number: 20210028115
    Abstract: Certain aspects of the present disclosure generally relate to an integrated device including a low parasitic middle-of-line (MOL) structure. The integrated device generally includes a plurality of semiconductor devices; an MOL structure disposed above the plurality of semiconductor devices and comprising a dielectric layer; a first barrier-less conductor extending between a first terminal of a semiconductor device in the plurality of semiconductor devices and into the MOL structure; and a first air gap disposed between a lateral surface of an upper portion of the first barrier-less conductor and the dielectric layer of the MOL structure.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 28, 2021
    Inventors: Junjing BAO, Peijie FENG, Haining YANG, Jun YUAN
  • Publication number: 20200303550
    Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Stanley Seungchul Song, Kern Rim, Da Yang, Peijie Feng
  • Patent number: 10763364
    Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: September 1, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Kern Rim, Da Yang, Peijie Feng
  • Publication number: 20200234999
    Abstract: Certain aspects of the present disclosure provide a transistor device, such as a fin field-effect transistor (finFET) device, and techniques for fabrication thereof. One example transistor device generally includes one or more semiconductor channel regions and a metal region disposed above the one or more semiconductor channel regions. The metal region has one or more gaps (e.g., air gaps) disposed therein.
    Type: Application
    Filed: January 17, 2019
    Publication date: July 23, 2020
    Inventors: Ye LU, Junjing BAO, Peijie FENG, Chenjie TANG
  • Patent number: 10700204
    Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 30, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Kern Rim, Da Yang, Peijie Feng
  • Patent number: 10686031
    Abstract: A capacitor includes first conductive fingers interdigitated with second conductive fingers at an Mx interconnect level, and third conductive fingers interdigitated with fourth conductive fingers at an Mx-1 interconnect level. The third conductive fingers are offset from the first conductive fingers. The second conductive fingers are offset from the fourth conductive fingers. The capacitor further includes fifth conductive fingers interdigitated with sixth conductive fingers at an Mx-2 interconnect level. The fifth conductive fingers are offset from the third conductive fingers. The sixth conductive fingers are offset from the fourth conductive fingers. The capacitor further includes seventh conductive fingers interdigitated with eighth conductive fingers at an Mx-3 interconnect level. The seventh conductive fingers are offset from the fifth conductive fingers. The eighth conductive fingers are offset from the sixth conductive fingers.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 16, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Peijie Feng, Junjing Bao, Ye Lu, Giridhar Nallapati
  • Publication number: 20200066858
    Abstract: A thin film transistor may include an insulating substrate and a layer of semiconductor material disposed over the insulating substrate. The thin film transistor may further include a gate electrode, a source electrode and a drain electrode disposed over the insulating substrate. The thin film transistor may further include a layer of first dielectric material disposed in between the gate electrode and the source and drain electrodes, and a layer of second dielectric material in contact with the layer of first dielectric material. The second dielectric material has a negative index.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Inventors: Junjing BAO, Peijie FENG, Ye LU, Bin YANG
  • Publication number: 20200058792
    Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.
    Type: Application
    Filed: August 17, 2018
    Publication date: February 20, 2020
    Inventors: Stanley Seungchul Song, Kern Rim, Da Yang, Peijie Feng
  • Publication number: 20190305077
    Abstract: A capacitor includes first conductive fingers interdigitated with second conductive fingers at an Mx interconnect level, and third conductive fingers interdigitated with fourth conductive fingers at an Mx-1 interconnect level. The third conductive fingers are offset from the first conductive fingers. The second conductive fingers are offset from the fourth conductive fingers. The capacitor further includes fifth conductive fingers interdigitated with sixth conductive fingers at an Mx-2 interconnect level. The fifth conductive fingers are offset from the third conductive fingers. The sixth conductive fingers are offset from the fourth conductive fingers. The capacitor further includes seventh conductive fingers interdigitated with eighth conductive fingers at an Mx-3 interconnect level. The seventh conductive fingers are offset from the fifth conductive fingers. The eighth conductive fingers are offset from the sixth conductive fingers.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Inventors: Peijie FENG, Junjing BAO, Ye LU, Giridhar NALLAPATI
  • Publication number: 20170207313
    Abstract: Nanowire metal-oxide semiconductor (MOS) Field-Effect Transistors (FETs) (MOSFETs) employing a nanowire channel structure employing recessed conductive structures for conductively coupling nanowire structures are disclosed. Conductive structures are disposed between adjacent nanowire structures to conductively couple nanowire structures. Providing conductive structures in the nanowire channel structure increases the average cross-sectional area of nanowire structures, as compared to a similar nanowire channel structure not employing conductive structures, thus increasing effective channel width and drive strength for a given channel structure height. The precision of a gate material filling process is also eased, because gate material does not have to be disposed in areas between adjacent nanowire structures occupied by conductive structures.
    Type: Application
    Filed: July 19, 2016
    Publication date: July 20, 2017
    Inventors: Stanley Seungchul Song, Jeffrey Junhao Xu, Kern Rim, Da Yang, Peijie Feng, Choh Fei Yeap
  • Publication number: 20170170268
    Abstract: Nanowire metal-oxide semiconductor (MOS) Field-Effect Transistors (FETs) (MOSFETs) employing a nanowire channel structure having rounded nanowire structures is disclosed. To reduce the distance between adjacent nanowire structures to reduce parasitic capacitance while providing sufficient gate control of the channel, the nanowire channel structure employs rounded nanowire structures. For example, the rounded nanowire structures provide for a decreased height from a center area of the rounded nanowire structures to end areas of the rounded nanowire structures. Gate material is disposed around rounded ends of the rounded nanowire structures to extend into a portion of separation areas between adjacent nanowire structures.
    Type: Application
    Filed: December 2, 2016
    Publication date: June 15, 2017
    Inventors: Stanley Seungchul Song, Peijie Feng, Kern Rim, Jeffrey Junhao Xu, Choh Fei Yeap
  • Patent number: 9577040
    Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Peijie Feng, Jianwei Peng, Yanxiang Liu, Shesh Mani Pandey, Francis Benistant
  • Patent number: 9559176
    Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: January 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Peijie Feng, Yanxiang Liu, Shesh Mani Pandey, Jianwei Peng, Francis Benistant
  • Publication number: 20160308005
    Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.
    Type: Application
    Filed: June 22, 2016
    Publication date: October 20, 2016
    Inventors: Peijie FENG, Jianwei PENG, Yanxiang LIU, Shesh Mani PANDEY, Francis BENISTANT
  • Publication number: 20160293718
    Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.
    Type: Application
    Filed: June 13, 2016
    Publication date: October 6, 2016
    Inventors: Peijie FENG, Yanxiang LIU, Shesh Mani PANDEY, Jianwei PENG, Francis BENISTANT