Abstract: A pixel structure including a first thin film transistor (TFT), a second TFT and a storage capacitor is provided. The source electrode of the first TFT is connected to the gate electrode of the second TFT, and the semiconductor layer of the second TFT protrudes out two opposite side of the gate electrode of the second TFT. A thin film transistor including a gate electrode, a capacitance compensation structure, a semiconductor layer, a dielectric layer, a drain electrode and a source electrode is also provided. The capacitance compensation structure is electrically connected to the gate electrode. The semiconductor layer partially overlaps the gate electrode, and extends to overlap the capacitance compensation structure.

Abstract: A liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer disposed between the first substrate and the second substrate, a common electrode layer disposed on the first substrate and a plurality of pixel structures disposed on the second substrate. Each of the pixel structure includes a first data line, a second data line, a third data line and at least a capacitance adjusting layer. The capacitance adjusting layer is disposed between the common electrode layer and the second data line.

Abstract: A display panel is provided, which includes a transparent substrate, a first thin film transistor (TFT), a second TFT, a transparent bottom electrode, a capacitance layer, a transparent top electrode, an opposite substrate and a display medium layer. The transparent substrate has a display region and a peripheral region. The display region has sub-pixel regions, and at least one sub-pixel region at least includes a capacitance region and a transistor region. The first and the second TFTs are disposed on the transistor region of the transparent substrate. The transparent bottom electrode, the capacitance layer and the transparent top electrode are sequentially disposed on the capacitance region of transparent substrate, in which the transparent bottom electrode is connected to a source/drain electrode of the first TFT, and the transparent top electrode is connected to a source/drain electrode of the second TFT.

Abstract: A pixel structure including a first thin film transistor (TFT), a second TFT and a storage capacitor is provided. The source electrode of the first TFT is connected to the gate electrode of the second TFT, and the semiconductor layer of the second TFT protrudes out two opposite side of the gate electrode of the second TFT. A thin film transistor including a gate electrode, a capacitance compensation structure, a semiconductor layer, a dielectric layer, a drain electrode and a source electrode is also provided. The capacitance compensation structure is electrically connected to the gate electrode. The semiconductor layer partially overlaps the gate electrode, and extends to overlap the capacitance compensation structure.

Abstract: A display panel includes a plurality of scan lines, a plurality of data lines, a plurality of power lines, a plurality of light emitting units, a plurality of first pixel circuits and a plurality of second pixel circuits. The plurality of light emitting units are arranged in an array and adapted to display different colors. In the organic light emitting units with the same color, some parts are connected to the first pixel circuits, and other parts are connected to the second pixel circuits. A first terminal and a second terminal of a first control transistor in the first pixel circuit are sequentially arranged on a forward direction of a first direction, and a first terminal and a second terminal of a second control transistor in the second pixel circuit are sequentially arranged on a reverse direction of the first direction.

Abstract: A pixel structure includes a plurality of data lines and a common line. The common line overlaps each data line, and is coupled with each data line to respectively form a first coupling capacitor, a second coupling capacitor, a third coupling capacitor, a fourth coupling capacitor, a fifth coupling capacitor, and a sixth coupling capacitor. The third coupling capacitor is smaller than the second coupling capacitor, and the fifth coupling capacitor is smaller than the fourth coupling capacitor.

Abstract: A display panel and a method for inspecting thereof are provided. The display panel includes a first signal circuit, a second signal circuit and a plurality of first resistor. The first signal circuit includes a plurality of first signal lines which disposes in parallel along a first direction and electrically connects to one another. The second signal circuit includes a plurality of second signal lines disposing in parallel along the first direction, and the second signal lines and the first signal lines are alternately disposed in parallel. Each of second signal lines is connected to at least a first resistor. The interval between the first signal line and the second signal line is smaller than 60 ?m and the difference between the resistances of the first signal line and the second signal line is ranged form 300 ohm to 30000 ohm.

Abstract: A pixel structure includes at least one first sub-pixel electrode, at least one second sub-pixel electrode, at least one common line, at least one first transistor electrically connected to the first sub-pixel electrode, and at least one second transistor electrically connected to the second sub-pixel electrode. The common line overlaps and is coupled respectively with the first sub-pixel electrode and the second sub-pixel electrode so as to respectively form a first storage capacitor and a second storage capacitor. The second storage capacitor is larger than the first storage capacitor. A first adjusting capacitor of the first transistor is larger than a second adjusting capacitor of the second transistor.

Abstract: A display panel includes at least twelve sub-pixels, arranged continuously in a row. In a scanning time of the display panel, sub-pixels respectively disposed at a 2nd, 3rd, 5th, 8th, 10th and 12th column have a first polarity, and sub-pixels respectively disposed at a 1st, 4th, 6th, 7th, 9th and 11th column have a second polarity. The first polarity is opposite to the second polarity.

Abstract: A pixel array, a pixel structure, and a driving method of a pixel structure are provided. The pixel structure includes a first scan line, a second scan line, a first common electrode line, a data line, a first active device, a second device, a first pixel electrode, and a second pixel electrode. The data line is intersected with the first scan line and the second scan line. The first active device is driven by the first scan line and connected to the data line. The second active device is driven by the second scan line and connected to the first common electrode line. The first pixel electrode is electrically connected to the data line through the first active device. The second pixel electrode is electrically connected to the data line through the first active device and electrically connected to the first common electrode line through the second active device.

Abstract: A pixel structure, a pixel array, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a pixel electrode, and a conductive bar pattern. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The conductive bar pattern is located on and electrically connected to the data line. The conductive bar pattern has a line width greater than or equal to a line width of the data line, and the conductive bar pattern and the pixel electrode are in the same layer.

Abstract: A pixel structure includes at least one first sub-pixel electrode, at least one second sub-pixel electrode, at least one common line, at least one first transistor electrically connected to the first sub-pixel electrode, and at least one second transistor electrically connected to the second sub-pixel electrode. The common line overlaps and is coupled respectively with the first sub-pixel electrode and the second sub-pixel electrode so as to respectively form a first storage capacitor and a second storage capacitor. The second storage capacitor is larger than the first storage capacitor. A first adjusting capacitor of the first transistor is larger than a second adjusting capacitor of the second transistor.

Abstract: A pixel structure includes a plurality of data lines and a common line. The common line overlaps each data line, and is coupled with each data line to respectively form a first coupling capacitor, a second coupling capacitor, a third coupling capacitor, a fourth coupling capacitor, a fifth coupling capacitor, and a sixth coupling capacitor. The third coupling capacitor is smaller than the second coupling capacitor, and the fifth coupling capacitor is smaller than the fourth coupling capacitor.

Abstract: A liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer disposed between the first substrate and the second substrate, a common electrode layer disposed on the first substrate and a plurality of pixel structures disposed on the second substrate. Each of the pixel structure includes a first data line, a second data line, a third data line and at least a capacitance adjusting layer. The capacitance adjusting layer is disposed between the common electrode layer and the second data line.

Abstract: A liquid crystal display panel includes an active device substrate, an opposite substrate and a liquid crystal layer. The active device substrate includes a plurality of scan lines, a plurality of data lines intersected with the scan lines, and a plurality of pixels. Each pixel at least includes a first, second, and third sub-pixel. The first, second, and third sub-pixels in each pixel are electrically connected with different data lines respectively, while being electrically connected with the same scan line. The opposite substrate having a common electrode is disposed above the active device substrate. Coupling capacitance (Cdc1) between the data line connected with the second sub-pixel and the common electrode is substantially greater than coupling capacitance (Cdc2) between the data line connected with the first sub-pixel and/or third sub-pixel and the common electrode. The liquid crystal layer is disposed between the active device substrate and the opposite substrate.

Abstract: A display panel includes at least twelve sub-pixels, arranged continuously in a row. In a scanning time of the display panel, sub-pixels respectively disposed at a 2nd, 3rd, 5th, 8th, 10th and 12th column have a first polarity, and sub-pixels respectively disposed at a 1st, 4th, 6th, 7th, 9th and 11th column have a second polarity. The first polarity is opposite to the second polarity.

Abstract: A non-volatile memory structure includes a substrate having two doped regions, a charge-trapping structure positioned substantially between the two doped regions, and a conductive structure positioned on the charge-trapping structure, wherein the charge-trapping structure includes a silicon-oxy-nitride layer and metallic nano-dots embedded in the silicon-oxy-nitride layer. The non-volatile memory structure formed by performing a first thermal oxidation process to form a high-k dielectric layer on a substrate, forming a metal-containing semiconductor layer including silicon or germanium on the high-k dielectric layer, forming a silicon layer on the metal-containing semiconductor layer, and performing a second thermal oxidation process to convert the metal-containing semiconductor layer to a silicon-oxy-nitride layer with embedded metallic nano-dots, wherein at least one of the first thermal oxidation process and the second thermal oxidation process is performed in a nitrogen-containing atmosphere.