Abstract: Disclosed is a gate drive circuit. The circuit includes multiple stages of gate drive units, and a gate drive unit in each stage includes a pull-up control module which outputs a pull-up control signal based on a previous stage of gate drive signal, a first pull-up module connected to the pull-up control module, a boost module connected to the first pull-up module, a second pull-up module connected to the first pull-up module, and a pull-down module connected to the first pull-up module and the second pull-up module.

Abstract: The present application discloses a method of performing photo alignment to a liquid crystal panel and a mask, the method including: disposing a mask in one side of a liquid crystal panel, the mask including at least two regions, the two regions makes incident lights passed and generating emission lights with different polarization directions respectively; making the incident light passed through the mask, to generate the emission lights with different polarization direction, and perform a photo alignment to the different regions of the liquid crystal panel. By the approach above, the process of the photo alignment is changed in the present application, thereby reducing the time of the photo alignment process and increase productivity.

Abstract: The invention provides a thin film transistor (TFT) array substrate and a display panel. The TFT array substrate is disposed with multiple pixels arranged in an array. Each pixel includes first through third sub-pixels sequentially arranged along a first direction. The first through third sub-pixels are connected to a same scan line. The TFT array substrate further is disposed with first through third data lines sequentially arranged along the first direction. The first through third data lines respectively are for driving the first through third sub-pixels. The first sub-pixel includes first and second areas, the second sub-pixel includes third and fourth areas, and the third sub-pixel includes fifth and sixth areas, arranged along a second direction. A voltage difference between a sub-pixel electrode in the sixth area and a common electrode is different from a voltage difference between a sub-pixel electrode in the fifth area and the common electrode.

Abstract: The present invention proposes a GOA circuit and a display device adopting the same. The GOA circuit includes thirteen transistors and a first capacitor. The GOA circuit can be driven in 2D and 3D driving modes to prolong charging time of each pixel. Each two GOA circuit units share a set of Nth stage start pulse signals, Nth stage gate pulse signals and eight clock pulse signals. Because the charging time of each pixel is prolonged, the display device can show images with better display quality.

Abstract: The present disclosure provides a COA array substrate and a display device. The COA array substrate includes a plurality of gate lines; a plurality of data lines; and a plurality of pixel units. Each of the pixel units includes a pixel electrode and a common electrode. The common electrode includes a lower common electrode and an upper common electrode. The lower common electrode is disposed on one of the data lines, and the upper common electrode is disposed on one of the gate lines. The present disclosure solves a light leakage problem and problems that an aperture ratio and a transmittance are low in a liquid crystal panel.

Abstract: Provided is an LTPS array substrate and a liquid crystal display panel, wherein the LTPS array substrate comprises: a first common electrode layer; a passivation layer, which is formed on the first common electrode layer, and has a first via hole formed therein; a pixel electrode layer, which is formed on the passivation layer; and a second common electrode layer, which is formed on the passivation layer, located between pixel electrodes corresponding to two adjacent sub-pixels in the pixel electrode layer, electrically isolated from the pixel electrode layer, and electrically connected to the first common electrode layer through the first via hole. The array substrate is capable of significantly enhancing the intensity of an electric field at an edge region of the adjacent sub-pixels, thereby increasing the transmittance at this region.

Abstract: Provided is a touch control display penal and a touch control circuit thereof. A test signal line and a touch control signal line are redesigned without any change in a conventional pixel structure, such that the touch control circuit as formed has both a test function and a touch detection function. Therefore, not only the manufacturing costs of an in-cell touch display device are effectively reduced, but the manufacturing procedure is simplified, and the yield rate of the touch display panel is improved as well.

Abstract: Disclosed is a liquid crystal display panel. An array substrate of the liquid crystal display panel comprises at least two pixel units. One pixel unit comprises: a scan line extending along a first direction; a data line extending along a second direction, different from the first direction; a pixel electrode; and a thin film transistor which is disposed in a functional connection between the data line and the pixel electrode. At least a part of the two adjacent pixel units are arranged mirror-symmetrically to each other. A new wire design is provided, so that a spacer can be arranged to avoid a PLN via hole, which effectively prevents the spacer of the panel from sliding into the PLN via hole while a liquid crystal cell is assembled or during a bending test procedure.

Abstract: Provided herein are compositions and methods related to modulation of progenitor microRNAs (pro-miRNAs), such as for the treatment of cancer.

Abstract: A GOA (Gate driver On Array) for an LCD (Liquid Crystal Display) device is disclosed herein. The LCD device comprises a plurality of scanning lines. The GOA circuit comprises a plurality of GOA units, which are cascaded with each other as a plurality of level GOA units. The (n)th level GOA unit comprises a clock circuit, a pull-down circuit, a bootstrap capacitor circuit, a pull-up circuit, and a pull-down sustain circuit, to improve the color shift issue of a Tri-gate.

Abstract: An LTPS array substrate and a method for producing the same are proposed. The method includes: forming an insulating layer, a semiconductor layer, and a first positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a source and a drain of the TFT on the polycrystalline silicon layer; forming a pixel electrode on the insulating layer and part of the source; forming a plain passivation layer on a source-drain electrode layer; forming a transparent electrode layer on the plain passivation layer so that the transparent electrode layer is connected to the gate, the source, and the drain via the contact hole. The use of masks in types and numbers in the LTPS technology can be reduced. Thus, both of the processes and the production costs are reduced.

Abstract: An LTPS array substrate and a method for producing the same are proposed. The method includes: forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a second insulating layer on the substrate of the polycrystalline silicon layer; forming a source and a drain of the TFT on the second insulating layer so that the source and the drain is electrically connected to the polycrystalline silicon layer via a contact hole. The method involves a reduced number of masks.

Abstract: An LTPS array substrate includes: a substrate on which a gate is disposed. An insulating layer and a polycrystalline silicon layer are disposed in sequence on the substrate and the gate. The insulating layer has an upper surface that is a plane. A source and a drain are disposed on the polycrystalline silicon layer and a pixel electrode is disposed on the insulating layer and a part of the drain. A plain passivation layer is disposed on the source and drain and includes a contact via formed therein at a location outside the polycrystalline silicon layer to expose a surface of one of the gate, the source, and the drain. A transparent electrode layer is disposed on the plain passivation layer to be electrically connected to the surface of the one of the gate, the source, and the drain that is exposed through the contact via.

Abstract: A method for manufacturing a LTPS array substrate includes: forming a source electrode and a drain electrode on a substrate, forming a poly-silicon layer in a first region and a second region of the substrate including the source electrode and the drain electrode, such that the poly-silicon layer of the first region has a thickness greater than that of the second region and the poly-silicon layer of the first region partially covers the source electrode and the drain electrode; passivating a surface of the poly-silicon layer in order to turn a part of the poly-silicon layer of the second region and the first region that is adjacent to the surface into an insulating layer; and forming a gate electrode on the insulating layer between the source electrode and the drain electrode. The LTPS technical process is simple and can reduce the producing costs.

Abstract: An LTPS array substrate includes a substrate; a gate disposed on the substrate; a first insulating layer, a polycrystalline silicon layer, and a second insulating layer sequentially disposed on the gate; a source and a drain disposed on the second insulating layer and are electrically connected to the polycrystalline silicon layer via first contact holes formed in the second insulating layer; a passivation layer disposed on the source, the drain, and the second insulating layer and including a second contact hole formed therein to expose a surface of the drain; a third insulating layer disposed on the passivation layer in such a way that the second contact hole is exposed outside the third insulating layer; and a pixel electrode disposed on the third insulation layer and electrically connected to the drain via the second contact hole.

Abstract: The present invention relates to a liquid crystal drive display device, including a display area and a liquid crystal drive circuit, the liquid crystal drive circuit including a plurality of stage GOA circuits, each stage GOA circuit includes a signal line and an auxiliary pull-down circuit, wherein the signal lines are divided into odd-numbered signal lines and even-numbered signal lines, the auxiliary pull-down circuits are divided into first auxiliary pull-down circuits and second auxiliary pull-down circuits; wherein the odd-numbered signal lines and the even-numbered signal lines are separately located on two sides of the display area, and the first auxiliary pull-down circuits and the second auxiliary pull-down circuits are also separately located on two sides of the display area, any two adjacent stage GOA circuits of the plurality of stage GOA circuits share the first auxiliary pull-down circuits and the second auxiliary pull-down circuits.

Abstract: The present invention provides a liquid crystal display panel, comprising: a control terminal of the first main thin film transistor on the nth row of the pixels connected to a branch of the scanning lines to which the nth row of the pixels correspond; the control terminal of the second main thin film transistor on the nth row of the pixels connected to a first branch of the scanning line of the (n+1)th row; the control terminal of the auxiliary thin film transistor on the (n+1)th row of pixels connected to a branch of the scanning lines of the (n+1)th row.

Abstract: A deskew display panel is disclosed in present invention. The deskew display panel includes a plurality of data lines arranged in a column direction, a plurality of scanning lines perpendicular to the column direction and intersecting the data lines; a sub-pixel array including a plurality of sub-pixels arranged in array, each sub-pixel including a transistor and disposed between any two neighboring scanning lines and any two neighboring data lines; the scanning lines disposed in the sub-pixel array and parallel to each other; sub-pixels in each row including a plurality of sub-pixel sets, each sub-pixel set including two sub-pixels, the sub-pixel including the transistor, gates of the transistors connected to two neighboring scanning lines respectively, sources of the transistors connected to the same data line, and drains of the transistors connected to a liquid crystal capacitor and a storage capacitor.

Abstract: The present embodiment is provided for a circuit of display panel, wherein comprising a signal wire extending along the first direction, a public electrode wire extending along the second direction, a pixel electrode, the first discharge circuit and the second discharge circuit, each signal wire is electrical connecting with the public electrode wire with the first discharge circuit and the second discharge circuit, the first discharge circuit and the second discharge circuit is in series, the pixel electrode is connecting on the intersection point between the first discharge circuit and the second discharge circuit.

Abstract: A liquid crystal display panel is provided, including: an array substrate; a color filter substrate opposite the array substrate, and a common electrode layer disposed on a side surface of the color filter substrate facing the array substrate of the color filter substrate; and a plurality of photo spacers disposed between the array substrate and the color filter substrate. The common electrode layer of the color filter substrate has a plurality of openings, and one end of each of the photo spacers is located on a corresponding opening.