Circuit of display panel

The present embodiment is provided for a circuit of display panel, wherein comprising a signal wire extending along the first direction, a public electrode wire extending along the second direction, a pixel electrode, the first discharge circuit and the second discharge circuit, each signal wire is electrical connecting with the public electrode wire with the first discharge circuit and the second discharge circuit, the first discharge circuit and the second discharge circuit is in series, the pixel electrode is connecting on the intersection point between the first discharge circuit and the second discharge circuit.

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Description
FIELD OF THE INVENTION

The present invention relates to a circuit of display panel.

BACKGROUND OF THE INVENTION

In the traditional display panel, a dummy pixel area, a public electrode circuit, electrostatic protection circuit, a fan-out and a bonding pad which is located inside or outside of the periphery line area. Therein, the dummy pixel area is provided for keep the stray capacitance, the impedance and other parameters around the display panel the same as the pixel unit inside the display panel, so as to prevent difference on display effect between the outside or inside of the display panel. Electrostatic protection circuit is electrically connecting to the public electrode wire with the signal wire (such as signal wire or date wire) by a special wire, so as to prevent the damage on the circuit of the display panel from electrostatic protection during the manufacture. Owing to the above circuit occupy a lot of space outside the display panel, so that is not good for the display panel with narrow border design.

Therefore, it's necessary to provide a circuit of display panel to overcome the about problem.

SUMMARY OF THE INVENTION

For resolve the above technology problem, the present embodiment is provided for a circuit of display panel, wherein comprising a signal wire extending along the first direction, a public electrode wire extending along the second direction, a pixel electrode, the first discharge circuit and the second discharge circuit, each signal wire is electrical connecting with the public electrode wire with the first discharge circuit and the second discharge circuit, the first discharge circuit and the second discharge circuit is in series, the pixel electrode is connecting on the intersection point between the first discharge circuit and the second discharge circuit.

Preferably, the first direction is vertical to the second direction.

Preferably, a plurality of pixel units are combined by the intersecting with two parallel signal wires adjoining and the two public electrode wires, the pixel units are arranging in array, and a pixel electrode is found from each pixel unit.

Preferably, the pixel unit is a dummy pixel unit.

Preferably, the first discharge circuit and the second discharge circuit comprising two thin film transistors, and each thin film transistor comprising a grid electrode, a source electrode and a drain electrode respectively, the grid electrode is electrically connecting with the drain electrode, the source electrode and the drain electrode of one thin film transistor are electrical connecting with the drain electrode and the source electrode of another thin film transistor of the first discharge circuit and the second discharge circuit to be a close loop.

Preferably, the connect point of the drain electrode and the source electrode in the first discharge circuit is electrical connecting with another connect point of the drain electrode and the source electrode in the second discharge circuit.

Preferably, the connect point is public electrode wire is electrically connecting with together, which the connect point of the drain electrode and the source electrode is form with the second discharge circuit and the first discharge circuit.

Preferably, the connect point is public electrode wire is electrically connecting with together, which the connect point of the drain electrode and the source electrode is form with the second discharge circuit and the first discharge circuit.

Preferably, the signal wire is selected from the signal scan wire or the date wire for transferring the display signal.

Preferably, the pixel electrode is a vertical distribution pixel electrode with a plurality of slots.

Compared to the prior art, the circuit of display panel of the present invention comprises a discharge circuit making from the thin film transistors of the dummy pixel unit to discharge for electrostatic protecting, and in the pixel electrode of the dummy pixel, the load of pixel unit around the display panel is keeping the same as the load of the pixel unit inside the display panel. Therefore, there is not install an independent electrostatic protection circuit outside the display panel, then to be an advantage for the border space of the display panel with narrow border design.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to illustrate more clearly the technology in the present embodiment of the prior art, the following making a sample introduction with the drawings.

FIG. 1 is a schematic perspective view of a circuit of display panel according to the present invention.

 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following describe is introducing the present invention.

Refer to FIG. 1, the circuit of display panel of the present invention 1 comprising a signal wire 10 extending along the first direction, a public electrode wire 12 extending along the second direction, a pixel electrode 14, the first discharge circuit 16 and the second discharge circuit 18. Each signal wire 10 is electrical connecting with the public electrode wire 12 with the first discharge circuit 16 and the second discharge circuit 18, the first discharge circuit 16 and the second discharge circuit 18 is in series, the pixel electrode 14 is connecting on the intersection point between the first discharge circuit 16 and the second discharge circuit 18. In the present embodiment, the first direction is vertical to the second direction, that is to say, the signal wire 10 is vertical to the public electrode wire 12.

A plurality of pixel units 20 are combined by the intersecting with two parallel signal wires 10 adjoining and the two public electrode wires 12. The pixel units 20 are arranging in array, and a pixel electrode 14 is found from each pixel unit 20. One of signal wire 10 is electrically connecting the public electrode wire 12 to be form the pixel unit 20, wherein the pixel unit 20 is assembling by the first discharge circuit 16 and the second discharge circuit 18 in series. The signal wire 10 is selected from the signal scan wire or the date wire for transferring the display signal. In the present embodiment, the pixel unit 20 is a dummy pixel unit.

The first discharge circuit 16 and the second discharge circuit 18 comprising two thin film transistors (TFT) 15, and each thin film transistor 15 comprising a grid electrode 150, a source electrode 152 and a drain electrode 154 respectively, the grid electrode 150 is electrically connecting with the drain electrode 154. The source electrode 152 and the drain electrode 154 of one thin film transistor 15 are electrical connecting with the drain electrode 154 and the source electrode 152 of another thin film transistor 15 of the first discharge circuit 16 and the second discharge circuit 18 to be a close loop. The connect point of the drain electrode 154 and the source electrode 152 in the first discharge circuit 16 is electrical connecting with another connect point of the drain electrode 154 and the source electrode 152 in the second discharge circuit 18. The grid electrode 150 of the TFT 15 in the first discharge circuit 16 is electrically connecting with the signal wire 10. One of drain electrode 154 in the first discharge circuit 16 is electrically connecting with the source electrode 152 on the connect point A, in the same way, one of drain electrode 154 in the second discharge circuit 18 is electrically connecting with the source electrode 152 on the connect point B. The connect point of the drain electrode 154 and the source electrode 152 is form with the second discharge circuit 18 and the first discharge circuit 16, the public electrode wire 12 is electrically connecting with the second discharge circuit 18 together on the connect point. The pixel electrode 14 is electrically connecting on the connect point with the first discharge circuit 16 and the second discharge circuit 18. In the present embodiment, the pixel electrode 14 is a vertical distribution pixel electrode 14 with a plurality of slots.

The circuit of display panel 1 of the present invention comprises a discharge circuit making from the thin film transistors of the dummy pixel unit to discharge for electrostatic protecting, and in the pixel electrode 14 of the dummy pixel, the load of pixel unit 20 around the display panel is keeping the same as the load of the pixel unit 20 inside the display panel. Therefore, there is not install an independent electrostatic protection circuit outside the display panel, then to be an advantage for the border space of the display panel with narrow border design.

Claims

1. A circuit of display panel, wherein comprising a signal wire extending along a first direction, a public electrode wire extending along a second direction, a pixel electrode, a first discharge circuit and a second discharge circuit, each signal wire is electrical connecting with the public electrode wire with the first discharge circuit and the second discharge circuit, the first discharge circuit and the second discharge circuit is in series, the pixel electrode is connecting on an intersection point between the first discharge circuit and the second discharge circuit, wherein the first discharge circuit and the second discharge circuit each comprises two thin film transistors, and each thin film transistor comprising a grid electrode, a source electrode and a drain electrode respectively, the grid electrode is electrically connecting with the drain electrode, the source electrode and the drain electrode of one thin film transistor are electrical connecting with the drain electrode and the source electrode of another thin film transistor of the first discharge circuit to be a close loop, the source electrode and the drain electrode of one thin film transistor are electrical connecting with the drain electrode and the source electrode of another thin film transistor of the second discharge circuit to be a close loop.

2. The circuit of display panel according to claim 1, wherein the first direction is vertical to the second direction.

3. The circuit of display panel according to claim 1, wherein a plurality of pixel units are combined by the intersecting with two parallel signal wires adjoining and two public electrode wires, the pixel units are arranging in array, and a pixel electrode is found from each pixel unit.

4. The circuit of display panel according to claim 1, wherein the pixel unit each is a dummy pixel unit.

5. The circuit of display panel according to claim 1, wherein a connect point of the drain electrode and the source electrode in the first discharge circuit is electrical connecting with another connect point of the drain electrode and the source electrode in the second discharge circuit.

6. The circuit of display panel according to claim 1, wherein a connect point is public electrode wire is electrically connecting with together, which the connect point of the drain electrode and the source electrode is form with the second discharge circuit and the first discharge circuit.

7. The circuit of display panel according to claim 1, wherein the signal wire is selected from a signal scan wire or a date wire for transferring the display signal.

Referenced Cited
U.S. Patent Documents
20060022204 February 2, 2006 Steer
20060044501 March 2, 2006 Mizusako
20100053489 March 4, 2010 Kang
Foreign Patent Documents
1766722 May 2006 CN
101097312 January 2008 CN
101285974 October 2008 CN
102331644 January 2012 CN
102629008 August 2012 CN
103794606 May 2014 CN
H11-52427 February 1999 JP
201009467 March 2010 TW
WO2004072941 August 2004 WO
Patent History
Patent number: 9940894
Type: Grant
Filed: Jan 22, 2015
Date of Patent: Apr 10, 2018
Patent Publication Number: 20160322019
Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD (Shenzhen)
Inventor: Peng Du (Guangdong)
Primary Examiner: Nan-Ying Yang
Application Number: 14/777,170
Classifications
Current U.S. Class: Incoherent Light Emitter Structure (257/79)
International Classification: G06F 3/038 (20130101); G09G 5/00 (20060101); G02F 1/136 (20060101); G09G 3/20 (20060101);