Patents by Inventor Peng Huang

Peng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11530660
    Abstract: A phase diagnosis method and apparatus. When it is verified that the location of an engine is valid, an oil injector performs spraying at a top center compression position; if no acceleration is detected after spraying, it indicates that a fault occurs; in order to detect whether it is a fault of phase deviation of the camshaft by 180 degrees, the oil sprayer performs spraying at the top center exhaust position and detects whether there is an acceleration; if an acceleration is detected, it indicates that the situation of the phase deviation of the camshaft by 180 degrees exists. In this way, the problem in the prior art of being unable to detect phase deviation when the phase of a camshaft is deviated by 180 degrees is solved.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: December 20, 2022
    Assignee: WEICHAI POWER CO.. LTD.
    Inventors: Dawei Song, Xuebin Wang, Peng Huang
  • Patent number: 11494215
    Abstract: Examples may include techniques to decrease a live migration time for a virtual machine (VM). Examples include selecting data to copy or not copy during a live migration of the VM from a source host server to a destination host server.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 8, 2022
    Assignee: Intel Corporation
    Inventors: Peng Huang, Liang Li, Xiaofeng Huang
  • Patent number: 11482488
    Abstract: A method for fabricating a memory is provided. The method includes providing a bit-line layer, on a semiconductor substrate and having bit lines arranged in the bit-line layer; providing a shielding layer, on the bit-line layer and having a conductive shielding structure arranged in the shielding layer. The conductive shielding structure is within a top-view projection area of the bit lines and is grounded. The method further includes providing a word-line layer, on the shielding layer and having word lines arranged in the word-line layer.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: October 25, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Peng Huang, Xue Hai Zhang, Chuan Miao Zhou
  • Publication number: 20220320212
    Abstract: A display substrate, a display panel, and a display device are provided. The display substrate includes: a base substrate; and a first transistor on the base substrate. The first transistor includes a first active layer, a first bottom gate electrode between the base substrate and the first active layer, and a first top gate electrode on a side of the first active layer away from the base substrate. A third gate insulating layer is provided between the first bottom gate electrode and the first active layer. The first active layer contains an oxide semiconductor material, and the third gate insulating layer contains a silicon oxide material. A surface of the first bottom gate electrode away from the base substrate is in direct contact with the silicon oxide material, and a surface of the first active layer close to the base substrate is in direct contact with the silicon oxide material.
    Type: Application
    Filed: September 30, 2020
    Publication date: October 6, 2022
    Inventors: Bingqiang Gui, Yang Yu, Peng Huang, Tao Gao, Wenqiang Li, Ke Liu
  • Publication number: 20220321900
    Abstract: A system and a method for compressing an image based on a FLASH in-memory computing array are provided. The system includes: a convolutional neural network for encoding of the FLASH in-memory computing array, a convolutional neural network for decoding based on the FLASH in-memory computing array, and a quantization module; the convolutional neural network for encoding based on the FLASH in-memory computing array is configured to encode an original image to obtain a feature image; the quantization module is configured to quantize the feature image to obtain a quantized image; the convolutional neural network for decoding based on the FLASH in-memory computing array is configured to decode the quantized image to obtain a compressed image.
    Type: Application
    Filed: December 31, 2019
    Publication date: October 6, 2022
    Inventors: Jinfeng Kang, Yachen Xiang, Peng Huang, Xiaoyan Liu, Runze Han
  • Publication number: 20220320269
    Abstract: This disclosure provides a display device, an array substrate, a thin film transistor and a fabrication method thereof. The thin film transistor includes an active layer, a gate insulating layer, a gate electrode, a dielectric layer, a source electrode and a drain electrode. The active layer has a channel region, doped regions at both sides of the channel region, and buffer regions each of which arranged between the corresponding doped region and the channel region, and a doping concentration of the buffer regions is less than that of the doped regions. The gate insulating layer is at a side of the active layer, covers the channel region and the buffer regions, and exposes the doped regions. The gate electrode is on a surface of the gate insulating layer facing away from the active layer.
    Type: Application
    Filed: January 4, 2021
    Publication date: October 6, 2022
    Inventors: Bingqiang GUI, Ke LIU, Peng HUANG, Tao GAO
  • Publication number: 20220320227
    Abstract: A display substrate, a display panel, and a display device are provided. The display substrate includes: a base substrate; a first semiconductor layer on the base substrate; and a second semiconductor layer on a side of the first semiconductor layer away from the base substrate. The display substrate further includes a plurality of thin film transistors on the base substrate, which at least include a first transistor, a second transistor and a third transistor. Each of the plurality of thin film transistors includes an active layer. The active layer of at least one of the first transistor and the second transistor is located in the second semiconductor layer and contains an oxide semiconductor material. The active layer of the third transistor is located in the first semiconductor layer and contains a polysilicon semiconductor material. At least one of the first transistor and the second transistor has a dual-gate structure.
    Type: Application
    Filed: September 30, 2020
    Publication date: October 6, 2022
    Inventors: Tao Gao, Peng Huang, Bingqiang Gui, Ke Yang
  • Publication number: 20220318612
    Abstract: A deep neural network based on analog FLASH computing array, includes a number of computing arrays, a number of subtractors, a number of activation circuit units and a number of integral-recognition circuit units. The computing array includes a number of computing units, a number of word lines, a plurality number of bit lines and a number of source lines. Each of the computing units includes a FLASH cell. The gate electrodes of the FLASH cells in the same column are connected to the same word line. The source electrodes of the FLASH cells in the same column are connected to the same source line, and the drain electrodes of the FLASH cells in the same row are connected to the same bit line. Each of the subtractors includes a positive terminal, a negative terminal and an output terminal.
    Type: Application
    Filed: December 31, 2019
    Publication date: October 6, 2022
    Inventors: Peng HUANG, Guihai YU, Jinfeng KANG, Yachen XIANG, Xiaoyan LIU, Lifeng LIU
  • Publication number: 20220277791
    Abstract: An operating circuit and an operating method of a resistive random-access memory are provided, the operating circuit includes: at least one capacitance connected in series with the resistive random-access memory, so that the resistive random-access memory is grounded through the at least one capacitance. The operating method includes: connecting at least one capacitance in series with a resistive random-access memory, so that the resistive random-access memory is grounded through the capacitance; applying a forming pulse voltage or a set pulse voltage on the resistive random-access memory to achieve a forming operation or a set operation of the resistive random-access memory.
    Type: Application
    Filed: August 2, 2019
    Publication date: September 1, 2022
    Applicant: Peking University
    Inventors: Peng HUANG, Yizhou ZHANG, Yulin FENG, Jinfeng KANG, Xiaoyan LIU, Lifeng LIU
  • Publication number: 20220263589
    Abstract: A digital pre-distortion processing method and an electronic device are provided. The method is performed by an electronic device and includes: detecting a standing wave status of an antenna of the electronic device; obtaining a calibration result through digital pre-distortion calibration in a case that the standing wave status satisfies a preset working condition; and determining whether to enable a digital pre-distortion function according to the calibration result.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 18, 2022
    Applicant: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Peng HUANG, Runpeng HUANG
  • Publication number: 20220248788
    Abstract: A functional clothing having improved pockets is provided. The functional clothing includes a clothing body, a first pocket, a card holder pocket, a second pocket and an inner pocket. The first pocket is disposed on the clothing body and has a first pocket space. The card holder pocket is disposed in the first pocket space, and the card holder pocket has at least one card holder pocket space. The second pocket is disposed on the clothing body and has a second pocket space. The inner pocket is disposed in the second pocket space, and the inner pocket has an inner pocket space.
    Type: Application
    Filed: May 24, 2021
    Publication date: August 11, 2022
    Inventors: KUO-PENG HUANG, Shu-Ching Tseng
  • Publication number: 20220240881
    Abstract: A device may obtain first information relating to one or more first lung nodules identified in first imaging of a chest of a patient and second information relating to one or more second lung nodules identified in second imaging of the chest of the patient. The device may provide the first information and the second information to a machine learning model. The device may determine, using the machine learning model, a risk of lung cancer associated with the patient based on an elapsed time between performance of the first imaging and the second imaging and differences between the first information and the second information. The risk of lung cancer may have an inverse correlation to the elapsed time and a direct correlation to the differences.
    Type: Application
    Filed: June 23, 2020
    Publication date: August 4, 2022
    Applicants: The Johns Hopkins University, Provincial Health Services Authority
    Inventors: Peng HUANG, Yuliang LI, Stephen LAM
  • Publication number: 20220230909
    Abstract: A method for making a deep trench isolation of a CIS device includes: growing a first epitaxial layer on a substrate; forming a hard mask layer on the first epitaxial layer; performing photolithography and etching processes to form deep trenches arranged longitudinally and transversely in the first epitaxial layer; forming a second epitaxial layer in the deep trenches; performing a thermal oxidation process to form a first oxide layer on the surface of the second epitaxial layer; completely filling the deep trenches with polysilicon; performing a back-etching process to expose sidewalls of the first oxide layer in the deep trenches; forming a second oxide layer on the top of the polysilicon; removing the hard mask layer and the first oxide layer above the second oxide layer; rapidly growing a third epitaxial layer; and performing a CMP process to form a deep trench isolation on the substrate.
    Type: Application
    Filed: January 17, 2022
    Publication date: July 21, 2022
    Applicants: Hua Hong Semiconductor (Wuxi) Limited, Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jialong LI, Peng HUANG, Xiao FAN, Wensheng QIAN
  • Publication number: 20220218691
    Abstract: Novel combination therapies involving nitroxoline, its analogue or pharmaceutically acceptable salt thereof with at least one additional anti-cancer chemotherapy or immunotherapy agent are described. Related kits, pharmaceutical compositions and methods of production are also described.
    Type: Application
    Filed: March 29, 2022
    Publication date: July 14, 2022
    Inventors: Ke PAN, Peng Huang, Qiang Li
  • Publication number: 20220218692
    Abstract: Novel combination therapies involving nitroxoline, its analogue or pharmaceutically acceptable salt thereof with at least one additional anti-cancer chemotherapy or immunotherapy agent are described. Related kits, pharmaceutical compositions and methods of production arlinee also described.
    Type: Application
    Filed: March 29, 2022
    Publication date: July 14, 2022
    Inventors: Ke PAN, Peng Huang, Qiang Li
  • Patent number: 11375614
    Abstract: The present disclosure provides a wiring structure, a display substrate and a display device, and belongs to the field of display technology. The wiring structure of the present disclosure comprises a body portion provided with hollow patterns; the body portion has a first side and a second side which are provided opposite to each other along an extending direction of the wiring structure, and both the first and second sides are wavy; the body portion comprises a plurality of conductive elements sequentially connected along the extending direction of the wiring structure; and in each conductive element, a length of a protruding portion on the first side in the extending direction of the wiring structure is different from that of a protruding portion on the second side in the extending direction of the wiring structure.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: June 28, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhifeng Zhan, Peng Huang, Yanxin Wang, Shuquan Yang, Wei Wang
  • Publication number: 20220199659
    Abstract: A method for making an isolation region of a CIS device includes: forming a block layer on a substrate, below the block layer being an oxide layer, below the oxide layer being a silicon nitride layer, and a shallow trench isolation being formed in the substrate; forming a hard mask layer on the surface of the block layer, the material of the hard mask layer is oxide; performing a photolithography process and an etching process to form an isolation region pattern in the hard mask layer; performing an ion implantation process to form an isolation region in the substrate corresponding to the isolation region pattern.
    Type: Application
    Filed: October 7, 2021
    Publication date: June 23, 2022
    Applicant: HUA HONG SEMICONDUCTOR (WUXI) LIMITED
    Inventors: Yuanyuan QUI, Zhenqiang GUO, Peng HUANG, Xiao FAN
  • Patent number: 11362291
    Abstract: A flexible substrate including a flexible base substrate, and a wiring layer and a back film on opposite sides of the flexible base substrate respectively. A side of the flexible base substrate facing away from the wiring layer is provided with a flat area including the back film and a bending area from which the back film is removed, the bending area is provided with an elastic reinforced film, and an elastic modulus of the elastic reinforced film is smaller than an elastic modulus of the back film. A display device including the flexible substrate and a method for manufacturing the flexible substrate are also provided.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: June 14, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yanxin Wang, Zhifeng Zhan, Peng Huang, Wei Wang, Shuquan Yang, Jiafan Shi
  • Patent number: 11340924
    Abstract: In an approach for JAVA Virtual Machine (JVM) heap memory tuning, one or more computer processors obtain a feature vector of an application running on the JVM. The one or more computer processors input the feature vector to a predictive model trained with historical application data collected in one or more production environments. The one or more computer processors receive an output of the predictive model based on the feature vector with at least one memory tuning recommendation for the JVM. The one or more computer processors tune the memory of the JVM based on the at least one memory tuning recommendation.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 24, 2022
    Assignee: International Business Machines Corporation
    Inventors: Hong Bing Zhang, Huan Da Wang, Wei Peng Huang, Yi Yao, Hong Chen
  • Publication number: 20220149137
    Abstract: A display substrate is provided. The display substrate includes: a base substrate; a light-shielding layer disposed on the base substrate, the light-shielding layer comprising a light-shielding region; and a pixel drive layer disposed on a side of the light-shielding layer away from the base substrate, the pixel drive layer including at least one first thin-film transistor, at least one second thin-film transistor, and a first electrode plate of at least one storage capacitor, wherein the first thin-film transistor is disposed in correspondence with the light-shielding region, the second thin-film transistor in correspondence with the light-shielding region, and the at least one first electrode plate are disposed in correspondence with the light-shielding region.
    Type: Application
    Filed: November 2, 2021
    Publication date: May 12, 2022
    Inventors: Yanqiang WANG, Tao GAO, Peng HUANG, Ke LIU, Yuanzheng GUO