Patents by Inventor Peng Lin

Peng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11968659
    Abstract: The present disclosure provides a method of scheduling for a UE. The method includes dividing M UEs into N groups, wherein a distance metric between each UE in a group and the center of the group does not exceed a first predetermined threshold, where M and N are positive integers; pairing the N groups, wherein a distance metric between centers of the two paired groups is greater than a second predetermined threshold; and in a case where there is a group paired with a group to which a first UE for which scheduling is to be performed belongs, scheduling transmissions in different directions respectively for the first UE and the second UE from the paired group on the same time-frequency resource. The present disclosure also provides a signal transmission method, a base station, a UE and a computer readable medium.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 23, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chuang Zhang, Di Su, Peng Lin, Chen Qian, Bin Yu
  • Patent number: 11964443
    Abstract: The invention relates to a method for connecting a connection piece to a U-shaped ring anchor for a head module for rail vehicles, the head module consisting predominantly of fiber-reinforced plastic material and having an outer shell and the ring anchor consisting of fiber-reinforced plastic material and being arranged in the roof region of the outer shell as a stiffening means. According to the method, connecting elements are fed through the dry or matrix-material-impregnated, unconsolidated fiber reinforcement structure of the ring anchor.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: April 23, 2024
    Assignees: CRRC QINGDAO SIFANG CO., LTD., CG RAIL—CHINESISCH-DEUTSCHES FORSCHUNGS- UND ENTWICKLUNGSZENTRUM FÜR BAHN- UND VERKEHRSTECHNIK DRESDEN GMBH
    Inventors: Jian Du, Peng Lin, Dongfang Chen, Zhengmin Zhang, Yonggui Zhang, Chunpeng Cao, Werner Hufenbach, Andreas Ulbricht
  • Patent number: 11967725
    Abstract: Embodiments of the present application provide a case of a battery, a battery, a power consumption device, and a method and device for preparing a battery. The case includes: an electrical chamber configured to accommodate a plurality of battery cells and a bus component, where at least one battery cell of the plurality of battery cells includes a pressure relief mechanism; a thermal management component configured to accommodate a fluid to adjust temperatures of the plurality of battery cells; and a collection chamber configured to collect, when the pressure relief mechanism is actuated, emissions from the battery cell provided with the pressure relief mechanism; where the thermal management component is configured to isolate the electrical chamber from the collection chamber. According to the technical solutions of the embodiments of the present application, the safety of the battery can be enhanced.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: April 23, 2024
    Assignee: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Xiaobo Chen, Fenggang Zhao, Yao Li, Peng Wang, Zhanyu Sun, Yongshou Lin
  • Publication number: 20240125016
    Abstract: The invention provides 3D-knitted spacer fabrics of high breathability and moisture management and methods of making the 3D-knitted spacer fabrics. The middle layer of the fabric is made of hydrophilic material, comprising two yarns, a blended thermo-fuse wicking yarn comprising hydrophilic fiber and thermo-fuse fiber, and a non-supportive hydrophilic functional wicking yarn. The top layer of the fabric comprises a hydrophilic yarn, and the third layer of the fabric comprises a hydrophobic yarn. The 3D-knitted spacer fabrics are useful in clothing and equipment for wear in high temperature environments.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 18, 2024
    Inventors: Tianqi ZHOU, Yuyan WANG, Rui LUO, Ling LIN, Zheng GU, Peng ZHOU, Jing XU
  • Publication number: 20240128178
    Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.
    Type: Application
    Filed: February 8, 2023
    Publication date: April 18, 2024
    Inventors: Yu-Hung LIN, Wei-Ming WANG, Su-Chun YANG, Jih-Churng TWU, Shih-Peng TAI, Kuo-Chung YEE
  • Publication number: 20240121766
    Abstract: Embodiments of the present disclosure provide method and apparatus for determining channel parameter. The determined channel parameter may be used for adaptive subband precoding. A method performed by a network device comprises determining at least one channel parameter for a subband related to a terminal device. The at least one channel parameter for the subband is calculated based on at least one channel parameter for a larger frequency band comprising the subband.
    Type: Application
    Filed: February 9, 2021
    Publication date: April 11, 2024
    Inventors: Zhao Wang, Zhenguo Ma, Rui He, Peng Lin
  • Publication number: 20240118355
    Abstract: The present disclosure relates to a wide-range perpendicular sensitive magnetic sensor and the method for manufacturing the same, the magnetic sensor includes a substrate, a plurality of magnetic tunnel junctions, a plurality of magnetic flux regulators, a first output port and a second output port.
    Type: Application
    Filed: September 6, 2023
    Publication date: April 11, 2024
    Applicant: DIGITAL GRID RES. INST., CHINA SOUTHERN PWR. GRID
    Inventors: Peng LI, Qiancheng LV, Bing TIAN, Zejie TAN, Zhiming WANG, Jie WEI, Renze CHEN, Xiaopeng FAN, Zhong LIU, Zhenheng XU, Senjing YAO, Licheng LI, Yuehuan LIN, Shengrong LIU, Bofeng LUO, Jiaming ZHANG, Xu YIN
  • Patent number: 11953568
    Abstract: The present disclosure relates to a wide-range perpendicular sensitive magnetic sensor and the method for manufacturing the same, the magnetic sensor includes a substrate, a plurality of magnetic tunnel junctions, a plurality of magnetic flux regulators, a first output port and a second output port.
    Type: Grant
    Filed: September 6, 2023
    Date of Patent: April 9, 2024
    Assignee: DIGITAL GRID RES. INST., CHINA SOUTHERN PWR. GRID
    Inventors: Peng Li, Qiancheng Lv, Bing Tian, Zejie Tan, Zhiming Wang, Jie Wei, Renze Chen, Xiaopeng Fan, Zhong Liu, Zhenheng Xu, Senjing Yao, Licheng Li, Yuehuan Lin, Shengrong Liu, Bofeng Luo, Jiaming Zhang, Xu Yin
  • Patent number: 11955401
    Abstract: A package structure includes a semiconductor device and an adhesive pattern. The adhesive pattern surrounds the semiconductor device, wherein an angle ? is formed between a sidewall of the semiconductor device and a sidewall of the adhesive pattern, 0°<?<90° wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hui Wang, Der-Chyang Yeh, Shih-Peng Tai, Tsung-Shu Lin, Yi-Chung Huang
  • Publication number: 20240113034
    Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.
    Type: Application
    Filed: February 8, 2023
    Publication date: April 4, 2024
    Inventors: Yu-Hung LIN, Wei-Ming WANG, Chih-Hao YU, PaoTai HUANG, Pei-Hsuan LO, Shih-Peng TAI
  • Patent number: 11947072
    Abstract: The system comprises a rainfall monitoring module, a self-calibration and rainfall measurement module, a central processing module, a water level monitoring module, and a drainage module. The rainfall monitoring module is configured to monitor rainfall and send a rainfall signal to the central processing module. The self-calibration and rainfall measurement module is configured to transmit ultrasonic signals and receive calibration echo signals to compute the calibrated flight time, and transmit ultrasonic signals to the water surface in the bucket and receive the measured echo signal reflected by the water surface to obtain the measured flight time under the control of the central processing module. The central processing module is configured to receive the rainfall signal to start the water level monitoring module and the self-calibration and rainfall measurement module, which are used to calculate the rainfall value and output it in a fixed format.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: April 2, 2024
    Assignee: Hainan Acoustics Laboratory, Institute of Acoustics, Chinese Academy of Sciences
    Inventors: Songbin Li, Mingyong Yuan, Peng Liu, Daoyou Lin
  • Publication number: 20240106084
    Abstract: Embodiments of the present application provide a battery cell, a battery, a power consumption device, and a method and device for producing a battery cell. The battery cell includes: a housing having an opening; an electrode assembly accommodated in the housing; an end cover configured to cover the opening and provided with an electrode terminal; and a support, disposed in the housing, where the support and the electrode assembly are arranged in a first direction, the support and the end cover are arranged in a second direction, and the first direction is perpendicular to the second direction, the support abuts against the electrode assembly in the first direction so as to limit the electrode assembly.
    Type: Application
    Filed: December 8, 2023
    Publication date: March 28, 2024
    Applicant: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Denghua LIN, Xinxiang CHEN, Zhijun GUO, Yulian ZHENG, Peng WANG, Haizu JIN
  • Publication number: 20240107691
    Abstract: A display device includes first and second display modules and first and second turning pieces that include a first coupling piece, a first turning piece, a second turning piece, and a third turning piece, a second coupling piece and a guiding device. When the first and second display modules are switched between folding and unfolding, the first turning piece pivots relative to the first coupling piece and the second turning piece, and the third turning piece pivots relative to the second coupling piece and the second turning piece. When the display module is switched from folded to unfolded, the other side of the first display module relative to the side is pulled, the side of the first display module is guided by one end of the guiding device and slides to the other end, the first and second display modules are symmetrically unfolded with the side edge as the center.
    Type: Application
    Filed: December 8, 2023
    Publication date: March 28, 2024
    Inventors: CHIEN-FENG CHANG, TSUNG-HUAI LEE, YU-HUNG HSIAO, CHAN-PENG LIN, SHANG-CHIEN WU
  • Publication number: 20240102955
    Abstract: A non-invasive time domain reflection probe calibration method includes: using different volume ratio of ethanol and deionized water mixed solution to calculate a test target's medium weight coefficient and waveguide length of the non-invasive time domain reflection probes; using different concentrations of NaCl solutions to calibrate a waveguide geometric dimensioning of the non-invasive time domain reflection probes; preparing compacted soil samples with known different moisture contents and densities, and calibrating a correlation parameter of compacted soil samples' dielectric constant and conductivity with moisture content and density. The method not only determines the sensitivity of the test target medium of the non-invasive time domain reflection probes, but also obtains the waveguide length and geometric dimensioning of the probe, and realizes an accurate test of moisture content and density of the soil.
    Type: Application
    Filed: July 28, 2023
    Publication date: March 28, 2024
    Applicants: China Jikan Research Institute Of Engineering Investigations And Design, Co.,Ltd, Xi'an Jiaotong University
    Inventors: Jie CAO, Yonglin YANG, Zaixin WAN, Peng GAO, Qingyi MU, Dongjing WANG, Yuanqiang ZHOU, Zhi LIU, Long ZHANG, Hui LI, Jian CHEN, Teng YANG, Lei RAN, Jiao LIN, Xiao DONG, Shuai LIU, Weiwei ZHAO
  • Patent number: 11942373
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chu-An Lee, Chen-Hao Wu, Peng-Chung Jangjian, Chun-Wen Hsiao, Teng-Chun Tsai, Huang-Lin Chao
  • Publication number: 20240096722
    Abstract: In an embodiment, a package includes a first device and a second device attached to a first redistribution structure, wherein the second device includes a second redistribution structure, a first die disposed over the second redistribution structure, a first encapsulant extending along sidewalls of the first die, a first via extending through the first encapsulant, a third redistribution structure disposed over the first encapsulant and including a first metallization pattern connecting to the first via, a second die disposed over the third redistribution structure, and a second encapsulant extending along sidewalls of the second die, the first die and the second die being free of through substrate vias. The package also includes a third encapsulant disposed over the first redistribution structure and surrounding sidewalls of the first device and the second device, wherein top surfaces of the second encapsulant and the third encapsulant are level with each other.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 21, 2024
    Inventors: Kuo-Chung Yee, Chia-Hui Lin, Shih-Peng Tai
  • Publication number: 20240096830
    Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Yi Huang, Yu-Hung Lin, Wei-Ming Wang, Chen Chen, Shih-Peng Tai, Kuo-Chung Yee
  • Patent number: D1018997
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: March 19, 2024
    Assignee: HONEYWELL INTERNATIONAL INC.
    Inventors: Zheng Gu, Peng Zhou, Wenbo Wang, Xiaojuan Zhu, Ling Lin, Zhao Xia Jin, Tiecheng Qu, Weiming Zhou, Yolanda Wang, Anncy Zhou
  • Patent number: D1018999
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: March 19, 2024
    Assignee: HONEYWELL INTERNATIONAL INC.
    Inventors: Ling Lin, Peng Zhou, Xiaojuan Zhu, Weiming Zhou, Zheng Gu, Lyndon Liu
  • Patent number: D1022792
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: April 16, 2024
    Assignee: HONEYWELL INTERNATIONAL INC.
    Inventors: Zheng Gu, Peng Zhou, Wenbo Wang, Xiaojuan Zhu, Ling Lin, Lyndon Liu