Patents by Inventor Peng Liu

Peng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200335589
    Abstract: A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.
    Type: Application
    Filed: July 1, 2020
    Publication date: October 22, 2020
    Inventors: Ya ping Chen, Hong Yang, Peng Li, Seetharaman Sridhar, Yunlong Liu, Rui Liu
  • Publication number: 20200335895
    Abstract: An electrical connector assembly includes a first connector and a second connector mateable with each other wherein each of the first connector and the second connector has an insulative housing essentially composed of a bottom wall, a side wall and a pair of end walls wherein all the bottom wall and the side wall are rectangular while the end walls are right triangular. The first connector and he second connector are coupled with each other in a complementary manner with the corresponding hypotenuses of the right triangles confronting each other. A sealing member of a frame structure is located at an interface between the coupled edges of the housings in an oblique manner.
    Type: Application
    Filed: April 22, 2020
    Publication date: October 22, 2020
    Inventors: TA-LUNG LIU, KUO-CHUN HSU, BIN PENG, JIAN-KUANG ZHU, TING-TING YIN, YU-JIA DENG, CHENG-JUN ZOU, ZHONG-BAO WU
  • Publication number: 20200334053
    Abstract: The present disclosure provides a method, computer system and computer program product for generating a conversation content. According to the method, a rule corresponding to a first component of a user interface can be obtained, wherein the first component represents one or more resources provided to a user, an operation for the first component can be determined based on the rule and a feature of the first component, a virtual component tree can be constructed according to the operation, wherein the virtual component tree depicts components to be included in the user interface and relationship between the components; and the user interface can be rendered based on the virtual component tree.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 22, 2020
    Inventors: Shu Chao Wan, Jing Jing Pan, Xin Peng Liu, Yiwen Huang, YE CUI
  • Publication number: 20200333771
    Abstract: A method is disclosed that includes the operations below: determining, by a processing unit, that arrival times of a lot arrived at N process stages are less than processing times of the lot predetermined to be processed at the N process stages, N being a positive integer; comparing, by the processing unit, idle times of multiple tools in the N process stages; and processing the lot with a first tool of the tools at each one of the N process stages, wherein the first tool of the tools has a shortest idle time.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ren-Chyi YOU, An-Wei PENG, Chang-Zong LIU, Yuang-Tsung CHEN
  • Patent number: 10811211
    Abstract: A method for making a carbon nanotube field emitter is provided. A carbon nanotube array and a cathode substrate are provided. The carbon nanotube array is heated to form a graphitized carbon nanotube array. A conductive adhesive layer is formed on a surface of the cathode substrate. One end of the graphitized carbon nanotube array is contact with the conductive adhesive layer. The conductive adhesive layer is solidified to fix the graphitized carbon nanotube array on the cathode substrate.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 20, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Peng Liu, Duan-Liang Zhou, Chun-Hai Zhang, Li Qian, Yu-Quan Wang, Xue-Wei Guo, Li-Yong Ma, Fu-Jun Wang, Shou-Shan Fan
  • Patent number: 10810153
    Abstract: The present invention provides a chip processing device and a method for chip processing using the same, where the device can program, detect, reset or inspect a plurality of chips, and meanwhile has one or more functions of programming, detecting, identifying, resetting or inspecting. The plurality of chips has different communication interfaces, and/or uses different communication protocols. The chip processing device can be configured to program, detect, identify, reset or inspect a chip after obtaining the model of the chip to be processed, thus having higher universality.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: October 20, 2020
    Assignee: APEX MICROELECTRONICS CO., LTD.
    Inventors: Meichao Qi, Jinxin Liu, Peng Lou, Bin Zhou, Hao Chen
  • Patent number: 10811519
    Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chang Huang, Fu-Peng Lu, Chun-Chang Liu, Chen-Chiu Huang
  • Publication number: 20200326599
    Abstract: An array substrate and a display device including the array substrate are provided. The array substrate includes: an upper electrode layer on a base substrate and including a first upper electrode strip and a second upper electrode strip; a lower electrode layer between the base substrate and the upper electrode layer. The lower electrode layer includes a portion that does not overlap the first upper electrode strip and the second upper electrode strip in a direction perpendicular to an upper surface of the base substrate. The array substrate includes a pixel electrode strip and a common electrode strip which are in a same layer and both correspond to a region between the first upper electrode strip and the second upper electrode strip.
    Type: Application
    Filed: March 15, 2018
    Publication date: October 15, 2020
    Inventors: Haoxiang FAN, Keke GU, Peng LI, Xiaoji LI, Zhe LI, Junhong LU, Wei ZHU, Peng QIN, Wenliang LIU
  • Publication number: 20200328869
    Abstract: Embodiments of the present invention provide a method and apparatus for transmitting and determining timing information, a storage medium, and a processor. The transmitting method includes: carrying timing information by using a demodulation reference signal (DMRS), where the timing information is used to indicate a terminal to determine a time domain location; and transmitting the DMRS carrying the timing information to the terminal.
    Type: Application
    Filed: December 13, 2019
    Publication date: October 15, 2020
    Inventors: Xing LIU, Peng HAO, Feng BI, Ting MIAO
  • Publication number: 20200327403
    Abstract: An all-optical neural network that utilizes light beams and optical components to implement layers of the neural network is disclosed herein. The all-optical neural network includes an input layer, zero or more hidden layers, and an output layer. Each layer of the neural network is configured to simulate linear and nonlinear operations of a conventional artificial neural network neuron on an optical signal. In an embodiment, the optical linear operation is performed by a spatial light modulator and an optical lens. The optical lens performs a Fourier transformation on the set of light beams and sums light beams with similar propagation orientations. The optical nonlinear operation is implemented utilizing a nonlinear optical medium having an electromagnetically induced transparency characteristic whose transmission of a probe beam of light is controlled by the intermediate output of a coupling beam of light from the optical linear operation.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 15, 2020
    Inventors: Shengwang DU, Junwei LIU, Ying ZUO, Bohan LI, Yujun ZHAO, Yue JIANG, Peng CHEN, You-Chiuan CHEN
  • Patent number: 10803395
    Abstract: Systems, computer-implemented methods, and computer program products to facilitate quantum domain computation of classical domain specifications are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an input transformation component that can be adapted to receive one or more types of domain-specific input data corresponding to at least one of a plurality of domains. The input transformation component can transform the one or more types of domain-specific input data to quantum-based input data. The computer executable components can further comprise a circuit generator component that, based on the quantum-based input data, can generate a quantum circuit.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: October 13, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marco Pistoia, Jay M. Gambetta, Antonio Mezzacapo, Richard Chen, Stephen Wood, Peng Liu, Shaohan Hu, Julia Elizabeth Rice, Ivano Tavernelli, Rudy Raymond Harry Putra, Panagiotis Barkoutsos, Nikolaj Moll
  • Patent number: 10795231
    Abstract: The present disclosure discloses an array substrate and its manufacturing method, a display panel and its manufacturing method, and a display device. The array substrate includes: a base substrate; a plurality of data lines; and a plurality of pixel units arranged on the base substrate, where each of the plurality of pixel units includes a plurality of subpixel units, and the plurality of subpixel units is in a one-to-one correspondence with the plurality of data lines, where each of the plurality of subpixel units includes a first subpixel unit and a second subpixel unit that are adjacently arranged, and the data line corresponding to the first subpixel unit and the data line corresponding to the second subpixel unit are both arranged at a position corresponding to a boundary between the first subpixel unit and the second subpixel unit.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 6, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Zhengkui Wang, Jian Sun, Yun Qiao, Han Zhang, Zhen Wang, Ruichao Liu, Jianjun Zhang, Peng Liu
  • Patent number: 10797253
    Abstract: A fabrication method and a fabrication assembly for a flexible display substrate are provided. The fabrication assembly for a flexible display substrate includes: a rigid base substrate, including a first engaging structure being on a surface of the rigid base substrate; and a protective film, including a first surface and a second surface opposite to each other, and including a second engaging structure being on the first surface. The second surface of the protective film is configured to be attached to a flexible base substrate; and the rigid base substrate and the protective film are configured to be detachably connected with each other by the first engaging structure and the second engaging structure.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: October 6, 2020
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jianqiang Bi, Ming Hua, Peng Li, Yuanfu Bao, Jinya Feng, Jie Ge, Lei Bai, Xuemin Liu, Zhen Li, Haiyan Yang, Jianguo Xing
  • Publication number: 20200314845
    Abstract: Provided is a method for indicating a resource location. The method includes: sending, by a first-type node, resource location information to a second-type node, the resource location information at least indicates a frequency-domain location of a resource, where the frequency-domain location includes at least one of: a frequency-domain location of a first resource or a frequency-domain location of a second resource, and the first resource or the second resource includes at least one of: a bandwidth part (BWP), a resource occupied by a physical downlink shared channel (PDSCH), or a common control resource set. Also provided are a device for indicating a resource location, and a method, device, terminal, base station, processor, and storage medium for receiving a resource location.
    Type: Application
    Filed: February 7, 2020
    Publication date: October 1, 2020
    Inventors: Ting MIAO, Feng BI, Peng HAO, Xing LIU
  • Publication number: 20200313051
    Abstract: The disclosure discloses an optoelectronic element comprising: an optoelectronic unit comprising a first metal layer, a second metal layer, and an outermost lateral surface; an insulating layer having a first portion overlapping the optoelectronic unit and extending beyond the lateral surface, and a second portion separated from the first portion in a cross-sectional view; and a first conductive layer formed on the insulating layer.
    Type: Application
    Filed: June 12, 2020
    Publication date: October 1, 2020
    Inventors: Cheng-Nan HAN, Tsung-Xian LEE, Min-Hsun HSIEH, Hung-Hsuan CHEN, Hsin-Mao LIU, Hsing-Chao CHEN, Ching-San TAO, Chih-Peng NI, Tzer- Perng CHEN, Jen-Chau WU
  • Publication number: 20200313029
    Abstract: Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 1, 2020
    Inventors: Chien-Yu Chen, Szu-Lin Cheng, Chieh-Ting Lin, Yu-Hsuan Liu, Ming-Jay Yang, Shu-Lu Chen, Tsung-Ting Wu, Chia-Peng Lin, Yun-Chung Na, Hui-Wen Chen, Han-Din Liu
  • Publication number: 20200308620
    Abstract: Provided herein are methods of using atomic force microscopy (AFM) to measure the adhesion force between a cell surface target and a ligand (e.g., an antibody) that binds to the cell surface target. Such adhesion force serves as an in vitro metric for predicting the in vivo tumor recognition and/or anti-tumor efficacy of antibody-directed nanomedicine.
    Type: Application
    Filed: October 26, 2018
    Publication date: October 1, 2020
    Applicant: Children's Medical Center Corporation
    Inventors: Marsha A. Moses, Peng Guo, Debra Auguste, Jiang Yang, Daxing Liu
  • Publication number: 20200308404
    Abstract: Provided are a composition, a cured polymer material formed from said composition, a method for forming a thermally conductive material on an article and an article having a thermally conductive material. Said thermally conductive material can be formed on an electronic device, and can be peeled off from said electronic device.
    Type: Application
    Filed: September 29, 2017
    Publication date: October 1, 2020
    Applicant: Dow Silicones Corporation
    Inventors: Zhihua LIU, Peng WEI, Hexiang YAN, Yi ZHAO, Qi CHEN, Junmin ZHU
  • Patent number: 10790261
    Abstract: A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Chia-Shen Cheng, Hao-Jan Pei, Philip Yu-Shuan Chung, Kuei-Wei Huang, Yu-Peng Tsai, Hsiu-Jen Lin, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu
  • Patent number: 10790312
    Abstract: A display panel and a display device are provided. The display panel includes a base substrate, the base substrate includes a display region and a non-display region, the display region includes a main display region and a peripheral display region, and the peripheral display region includes an irregular display region; the non-display region includes a first region and a second region, the first region is adjacent to the irregular display region, and the second region is adjacent to other regions of the peripheral display region than the irregular display region; the display region includes at least one signal line, the non-display region includes at least one functional circuit and at least one wire, and the at least one functional circuit is coupled to the at least one signal line via the at least one wire.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 29, 2020
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yun Qiao, Zhen Wang, Lele Cong, Zhengkui Wang, Jianjun Zhang, Han Zhang, Wenwen Qin, Fei Huang, Xiaozhou Zhan, Peng Liu, Jian Sun