Patents by Inventor Peng Zou

Peng Zou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12289898
    Abstract: A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: April 29, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Peng Zou, Syrus Ziai
  • Publication number: 20250132677
    Abstract: This application is directed to providing rail voltages for an electronic system. The electronic system includes an array of voltage regulator cells and a plurality of reference circuits. The array of voltage regulator cells is configured to provide a plurality of voltage regulator sets, and each voltage regulator set is configured to output a respective rail voltage to a respective power rail of a plurality of power rails. The plurality of reference circuits are coupled to the array of voltage regulator cells. Each reference circuit is shared by, and configured to provide a respective reference voltage to, one or more respective voltage regulator cells of a respective voltage regulator set. The respective voltage regulator set is configured to generate the respective rail voltage based on the respective reference voltage.
    Type: Application
    Filed: October 17, 2024
    Publication date: April 24, 2025
    Inventors: Peng Zou, Gang Ren, Sujith Dermal
  • Publication number: 20250130604
    Abstract: This application is directed to an electronic device having a configurable group of voltage regulator cells. The electronic device includes a group of voltage regulator cells operating based on parameter settings of individual voltage regulator cells, output a rail voltage, and provide the rail voltage to multiple power rails. The electronic device includes a memory component coupled to the group of voltage regulator cells. The memory component stores an encoding table including multiple register files, and a register file defines parameter settings for the individual voltage regulator cells of the group of voltage regulator cells. The electronic device includes a setting interface for receiving a parameter setting signal applied to select the register file among the multiple register files for defining the parameter settings for the group of voltage regulator cells. The electronic device includes a substrate where the group of voltage regulator cells and the setting interface are integrated.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 24, 2025
    Inventors: Peng Zou, Gang Ren, Sujith S. Dermal
  • Publication number: 20250132297
    Abstract: This application is directed to providing a thermal path for a circuit package. The circuit package includes a plurality of chiplets. The circuit package further includes a substrate coupled to the plurality of chiplets. The circuit package further includes a processor coupled to the plurality of chiplets through the substrate. The circuit package further includes a printed circuit board coupled to the plurality of chiplets and including a thermal path between a first side and a second side of the printed circuit board. The thermal path is configured to dissipate heat from the plurality of chiplets to ambient.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 24, 2025
    Inventors: Gang Ren, Peng Zou, Sujith S. Dermal
  • Publication number: 20250132679
    Abstract: This application is directed to a dual-loop control scheme including multiple voltage regulation loops configured to stabilize an output voltage. The voltage regulation loops include a first loop and a second loop. The first loop includes a feedback signal sensing component for sensing the output voltage. The first loop includes an error amplifier component for determining a voltage difference between the output voltage fed to the error amplifier component and a reference voltage. The first loop further includes a loop compensation network for generating a voltage compensation signal. The voltage regulations loops include a second loop for stabilizing output voltage after the transient voltage conditions have been compensated for by the first loop. The second loop includes a transition sensor module for detecting a transient voltage in the first loop's output voltage. And the second loop includes an amplification module for generating a regulation-based-adjustment signal.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 24, 2025
    Inventors: Gang Ren, Peng Zou, Sujith S. Dermal
  • Patent number: 12281978
    Abstract: A spectroscopic assembly may include a spectrometer. The spectrometer may include an illumination source to generate a light to illuminate a sample. The spectrometer may include a sensor to obtain a spectroscopic measurement based on light, reflected by the sample, from the light illuminating the sample. The spectroscopic assembly may include a light pipe to transfer the light reflected from the sample. The light pipe may include a first opening to receive the spectrometer. The light pipe may include a second opening to receive the sample, such that the sample is enclosed by the light pipe and a base surface when the sample is received at the second opening. The light pipe may be associated with aligning the illumination source and the sensor with the sample.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: April 22, 2025
    Assignee: VIAVI Solutions Inc.
    Inventors: Curtis R. Hruska, Peng Zou, Benjamin F. Catching, Marc K. Von Gunten, Valton Smith
  • Publication number: 20250096117
    Abstract: Passive components located outside the IC increase the area of the package and are connected to the circuits inside the IC by long electrical paths that may have high resistance as well as parasitic inductance and capacitance. An IC includes interconnect layers on a surface of a substrate comprising circuits, and the interconnect layers include stacked thin-film inductors formed in interconnect layers to provide noise protection for input signals provided to circuits in the IC while reducing an area of an IC package. The stacked thin-film inductors include a first thin-film inductor stacked between a second thin-film inductor and the surface of the substrate in a direction orthogonal to the surface of the substrate. The thin-film inductors can be formed of layers of magnetic material around a linear interconnect. The interconnect layers may be formed in a back end of line process on one surface of a substrate.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 20, 2025
    Inventors: Anshih Tseng, Peng Zou, Joseph Dibene, Gerard Williams
  • Patent number: 12161976
    Abstract: Provided by the present invention is a method for preparing a porous polymer semipermeable membrane, wherein a hydrophobic polynorbornene polymer and a hydrophilic small-molecule crosslinking agent containing a thiol functional group are mixed and dissolved in a solvent capable of dissolving both of them to obtain a coating solution; the coating solution is applied onto the surface of a biosensor electrode and dried such that the hydrophobic component and the hydrophilic component undergo phase separation; then, a membrane is formed and crosslinking is carried out, the unreacted hydrophilic small-molecule crosslinking agent is removed, and re-drying is carried out to obtain a porous polymer semipermeable membrane; also disclosed is a product.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: December 10, 2024
    Assignee: Dreisam (Beijing) Medical Technology Co., Ltd.
    Inventor: Peng Zou
  • Publication number: 20240372772
    Abstract: This application provides a communication method and apparatus in a high-frequency scenario. The method includes: A transmit-end device may modulate S bitstreams according to a mapping rule corresponding to a first modulation scheme for a higher-order modulation signal to be received by a receive-end device, to generate M lower-order modulation signals, where S is equal to 1 or M, and M is an integer greater than or equal to 2; and then send the M lower-order modulation signals through a line of sight LOS channel, so that a modulation order of a signal transmitted by a transmit end can be reduced.
    Type: Application
    Filed: July 1, 2024
    Publication date: November 7, 2024
    Inventors: Meng Shi, Rongkuan Liu, Jiayin Zhang, Peng Zou
  • Publication number: 20240356793
    Abstract: Embodiments of this application disclose a modulation method, a demodulation method, and a related apparatus. A first communication apparatus can ensure, by performing technical solutions of this application, a shaping gain brought by using probabilistic constellation shaping modulation in a high-frequency scenario. The method in embodiments of this application includes: The first communication apparatus determines probability distributions of constellation points in a target probabilistic shaping constellation diagram based on a Maxwell-Boltzmann distribution parameter and a phase noise parameter. The first communication apparatus modulates a first original bit stream and a second original bit stream based on the probability distributions of the constellation points in the target probabilistic shaping constellation diagram, to obtain a first quadrature amplitude modulation QAM symbol stream.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 24, 2024
    Inventors: Meng Shi, Peng Zou, Jiayin Zhang
  • Publication number: 20240356790
    Abstract: Embodiments of this application disclose a modulation method. A first communication apparatus generates a first symbol stream based on a symbol type quantity, a probability distribution corresponding to a first symbol of each symbol type, a bit quantity corresponding to each first symbol, and a first original bit stream, the bit quantity corresponding to each first symbol is a bit quantity required by each first symbol that is represented by using a bit, and first symbols of different symbol types correspond to different probability distributions and/or different signal amplitudes; and the first communication apparatus generates a first quadrature amplitude modulation (QAM) symbol stream based on the first symbol stream and a second original bit stream.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 24, 2024
    Inventors: Meng SHI, Peng ZOU, Jiayin ZHANG
  • Patent number: 12117214
    Abstract: A compressor includes a housing, and a drive assembly, a compression assembly and an expansion assembly which are provided in the housing; the compression assembly is connected to and driven by the drive assembly, and is configured to perform multi-stage compression on a refrigerant under drive of the drive assembly; the expansion assembly is connected to the drive assembly and is configured to expand the refrigerant compressed by the compression assembly. A refrigeration cycle device includes the above-mentioned compressor.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 15, 2024
    Assignee: Gree Green Refrigeration Technology Center Co., Ltd. of Zhuhai
    Inventors: Yusheng Hu, Huijun Wei, Peng Zou, Ouxiang Yang, Jian Wu
  • Publication number: 20240258364
    Abstract: An integrated circuit (IC) package, including an integrated circuit (IC) die including an input/output (I/O) pad, and a vertical thin-film inductor (TFI) extending vertically substantially from the I/O pad to a solder bump.
    Type: Application
    Filed: December 6, 2023
    Publication date: August 1, 2024
    Inventors: Anshih TSENG, Peng ZOU, Joseph DIBENE, Gerard WILLIAMS
  • Publication number: 20240105762
    Abstract: A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 28, 2024
    Inventors: Peng Zou, Syrus Ziai
  • Patent number: 11925460
    Abstract: A biosensor for determining an analyte is disclosed. The sensor has a sensor module covered at least partially by a biocompatibility layer. The biocompatibility layer has a polymer having —CO—NR1R2 side groups, wherein R1 and R2 are independently selected from —H and C1 to C6 alkyl. A method for producing the biosensor, as well as to uses and methods of using related to the biosensor, are also disclosed.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: March 12, 2024
    Assignee: Roche Diabetes Care, Inc.
    Inventor: Peng Zou
  • Publication number: 20240072023
    Abstract: An aspect relates to a method of forming an integrated circuit (IC) package, including: forming a thin-film inductor (TFI) over a first dummy carrier wafer; attaching an integrated circuit (IC) die to and over the TFI; attaching a second dummy carrier wafer to and over the IC die; removing the first dummy carrier wafer from the TFI; attaching at least one solder bump to and under the TFI; and removing the second dummy carrier wafer from the IC die. Another aspect relates to a method of forming an IC package, including forming a first redistribution layer (RDL) over a through-silicon via (TSV); forming a second RDL under the TSV; forming a thin-film inductor (TFI) over the first RDL; and attaching at least one integrated circuit (IC) die to the second RDL or the TFI.
    Type: Application
    Filed: February 22, 2023
    Publication date: February 29, 2024
    Inventors: Anshih TSENG, Peng ZOU
  • Patent number: 11881783
    Abstract: An electronic device has a power rail that is driven by voltage regulators and provides a rail voltage. Each voltage regulator has an output interface electrically coupled to the power rail to deliver up to a predefined regulator current to the power rail. In each voltage regulator, a voltage regulator controller has an input coupled to the output interface by a feedback path and controls a drive path coupled to the output interface. A bypass unit is coupled to the drive path and voltage regulator controller and operates in a standby mode or an operational mode. In the standby mode, the bypass unit bypasses the feedback path and the respective voltage regulator does not deliver current to the power rail, while in the operational mode, the bypass unit does not bypass the feedback path and the respective voltage regulator delivers up to the predefined regulator current to the power rail.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: January 23, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Peng Zou, Xijian Lin, Gang Ren, Joseph Dibene, Syrus Ziai
  • Patent number: 11855124
    Abstract: A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: December 26, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Peng Zou, Syrus Ziai
  • Publication number: 20230387181
    Abstract: A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.
    Type: Application
    Filed: April 13, 2023
    Publication date: November 30, 2023
    Inventors: Peng ZOU, Syrus ZIAI
  • Publication number: 20230311068
    Abstract: Provided by the present invention is a method for preparing a porous polymer semipermeable membrane, wherein a hydrophobic polynorbornene polymer and a hydrophilic small-molecule crosslinking agent containing a thiol functional group are mixed and dissolved in a solvent capable of dissolving both of them to obtain a coating solution; the coating solution is applied onto the surface of a biosensor electrode and dried such that the hydrophobic component and the hydrophilic component undergo phase separation; then, a membrane is formed and crosslinking is carried out, the unreacted hydrophilic small-molecule crosslinking agent is removed, and re-drying is carried out to obtain a porous polymer semipermeable membrane; also disclosed is a product.
    Type: Application
    Filed: September 8, 2021
    Publication date: October 5, 2023
    Inventor: Peng Zou