Patents by Inventor Perrine Batude

Perrine Batude has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200203229
    Abstract: Production of a device with superimposed levels of components including in this order: a) providing on a given level N1 provided with one or more components produced at least partially in a first semiconductor layer: a stack including a second semiconductor layer capable of receiving at least one transistor channel of level N2 above said given level N1, said stack including a so-called ground plane layer made of conductor or semiconductor material or doped semiconductor material situated between the first semiconductor layer and the second semiconductor layer as well as an insulator layer separating the ground plane layer from the second semiconductor layer, one or more islands being defined in the second semiconductor layer, b) forming a gate of a transistor on at least one island among said one or more islands, c) defining by etching distinct portions in the second semiconductor ground plane layer so as to free a space around at least one first etched portion of the ground plane layer arranged under an
    Type: Application
    Filed: December 17, 2019
    Publication date: June 25, 2020
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine BATUDE, Francois Andrieu
  • Publication number: 20200203422
    Abstract: A method of manufacturing an optoelectronic device, including the steps of: a) providing an active diode stack comprising a first doped semiconductor layer of a first conductivity type and a second doped semiconductor layer of the first conductivity type, coating the upper surface of the first layer; b) arranging a third semiconductor layer on the upper surface of the active stack; c) after step b), forming at least one MOS transistor inside and on top of the third semiconductor layer; and d) after step b), before or after step c), forming trenches vertically extending from the upper surface of the third layer and emerging into or onto the upper surface of the first layer and delimiting a plurality of pixels, each including a diode and an elementary diode control cell.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 25, 2020
    Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Perrine Batude, Hubert Bono
  • Patent number: 10651202
    Abstract: An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: May 12, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francois Andrieu, Perrine Batude, Maud Vinet
  • Patent number: 10586740
    Abstract: Method for producing a device provided with FinFET transistors, comprising the following steps: a) making amorphous and doping a first portion of a semiconductor in via a tilted beam oriented toward a first lateral face of the fin, while retaining a first crystalline semiconductor block against a second lateral face of the fin, then b) carrying out at least one recrystallization annealing of said first portion, then c) making amorphous and doping a second portion via a tilted beam oriented toward the second lateral face of the fin, while retaining a second crystalline semiconductor block against said first lateral face of the fin, then d) carrying out at least one recrystallization annealing of the second portion.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 10, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Benoit Mathieu, Perrine Batude
  • Patent number: 10553702
    Abstract: A method for producing a microelectronic device with one or more transistor(s) including forming a first gate on a region of a semiconductor layer, forming a first cavity in the semiconductor layer, the first cavity having a wall contiguous with the given region, filling the first cavity in such a way as to form a first semiconductor block wherein a source or drain region of the first transistor is capable of being produced, by epitaxial growth of a first semiconductor material in the first cavity, the growth being carried out such that a first zone of predetermined thickness of the layer of first semiconductor material lines the wall contiguous with the given region, epitaxial growth of a second zone made of a second semiconductor material on the first zone.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: February 4, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine Batude, Nicolas Posseme
  • Publication number: 20200035561
    Abstract: Production of a 3D microelectronic device including: assembling a structure comprising a lower level with a component partially formed in a first semiconductor layer with a support provided with a second semiconductor layer in which a transistor channel of an upper level is capable of being produced, the second semiconductor layer being capped with a dielectric material layer capable of forming a gate dielectric, forming a capping layer arranged on the dielectric material layer, and potentially capable of forming a lower gate portion of the transistor, defining a gate dielectric zone and an active zone of said transistor by etching the dielectric material layer and the second semiconductor layer, the capping layer protecting said dielectric material layer during this etching.
    Type: Application
    Filed: July 29, 2019
    Publication date: January 30, 2020
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine BATUDE, Francois ANDRIEU, Maud VINET
  • Patent number: 10497627
    Abstract: A method is provided for forming a transistor from a stack including the following successive layers: an electrically insulating layer, an active zone including at least one semiconductor layer, and a gate, sides of which are configured to be covered by at least one spacer, the method including: a phase of forming lateral cavities; and forming a raised drain and a raised source that fill the lateral cavities by growing the semiconductor layer via epitaxy, the forming of the lateral cavities includes, after a step of partially removing the semiconductor layer: forming a sacrificial layer, partially removing the sacrificial layer; forming spacers against the sides of the gate resting on a residual sacrificial layer; and totally removing the residual sacrificial layer in order to form the lateral cavities.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: December 3, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Laurent Brunet, Perrine Batude
  • Patent number: 10319628
    Abstract: A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: June 11, 2019
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Fabien Deprat, Perrine Batude, Laurent Brunet, Claire Fenouillet-Beranger, Maud Vinet
  • Publication number: 20190157300
    Abstract: Integrated circuit provided with several superimposed levels of transistors including: an upper level provided with transistors with a rear gate electrode laid out on a first semiconducting layer and a second semiconducting layer, a first transistor among said transistors of said upper level being provided with a contact pad traversing the second semiconducting layer, said contact pad being connected to a connection zone arranged between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line arranged on the side of a front face of the second semiconducting layer opposite to said rear face.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 23, 2019
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francois ANDRIEU, Perrine BATUDE, Maud VINET
  • Publication number: 20190157164
    Abstract: Method for producing a device provided with FinFET transistors, comprising the following steps: a) making amorphous and doping a first portion of a semiconductor in via a tilted beam oriented toward a first lateral face of the fin, while retaining a first crystalline semiconductor block against a second lateral face of the fin, then b) carrying out at least one recrystallization annealing of said first portion, then c) making amorphous and doping a second portion via a tilted beam oriented toward the second lateral face of the fin, while retaining a second crystalline semiconductor block against said first lateral face of the fin, then d) carrying out at least one recrystallization annealing of the second portion.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 23, 2019
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Benoit MATHIEU, Perrine BATUDE
  • Publication number: 20190148367
    Abstract: Production of an integrated circuit provided with several superposed levels of transistors, comprising: providing a structure provided with transistors of a lower level covered by an insulating layer itself covered by a stack with a first doped semi-conducting layer according to a doping of a first type, and a second doped semi-conducting layer according to a doping of opposite type, the first doped semi-conducting layer and the second doped semi-conducting layer being superposed and in contact with one another, etching the stack so as to form, on the insulating layer, a first block and a second block, then, removing in a given zone of the second block, the second given doped semi-conducting layer, forming a first gate on the second doped semi-conducting layer of the first block and a second gate on the first doped semi-conducting layer of the second block.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 16, 2019
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Pierre Colinge, Sylvain Barraud, Perrine Batude
  • Patent number: 10170621
    Abstract: Method of making a transistor, comprising the following steps: make a gate and a first spacer on a first channel region of a first crystalline semiconducting layer; make first crystalline semiconductor portions on the second source and drain regions; make the second regions amorphous and dope them; recrystallise the second regions and activate the dopants present in the second regions; remove the first portions; make a second spacer thicker than the first spacer; make second doped crystalline semiconductor portions on the second regions, said second portions and the second regions of the first layer together form the source and drain of the transistor.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: January 1, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Perrine Batude, Flavia Piegas Luce
  • Patent number: 9966453
    Abstract: Method including the steps consisting in: forming source and drain semiconductor blocks comprising a first layer based on a first crystalline semiconductor material surmounted by a second layer (16) based on a second crystalline semiconductor material different from the first semiconductor material, making amorphous and selectively doping the second layer (16) by means of one or more implantation(s), carrying out a recrystallisation of the second layer and an activation of dopants by means of at least one thermal annealing.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: May 8, 2018
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Shay Reboh, Perrine Batude, Frederic Mazen, Benoit Sklenard
  • Publication number: 20180090366
    Abstract: A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 29, 2018
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Fabien DEPRAT, Perrine BATUDE, Laurent BRUNET, Claire FENOUILLET-BERANGER, Maud VINET
  • Publication number: 20170345931
    Abstract: Method of making a transistor, comprising the following steps: make a gate and a first spacer on a first channel region of a first crystalline semiconducting layer; make first crystalline semiconductor portions on the second source and drain regions; make the second regions amorphous and dope them; recrystallise the second regions and activate the dopants present in the second regions; remove the first portions; make a second spacer thicker than the first spacer; make second doped crystalline semiconductor portions on the second regions, said second portions and the second regions of the first layer together form the source and drain of the transistor.
    Type: Application
    Filed: May 23, 2017
    Publication date: November 30, 2017
    Inventors: Shay REBOH, Perrine BATUDE, Flavia PIEGAS LUCE
  • Publication number: 20170301692
    Abstract: A method for producing a microelectronic device with one or more transistor(s) including forming a first gate on a region of a semiconductor layer, forming a first cavity in the semiconductor layer, the first cavity having a wall contiguous with the given region, filling the first cavity in such a way as to form a first semiconductor block wherein a source or drain region of the first transistor is capable of being produced, by epitaxial growth of a first semiconductor material in the first cavity, the growth being carried out such that a first zone of predetermined thickness of the layer of first semiconductor material lines the wall contiguous with the given region, epitaxial growth of a second zone made of a second semiconductor material on the first zone.
    Type: Application
    Filed: April 12, 2017
    Publication date: October 19, 2017
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine BATUDE, Nicolas POSSEME
  • Patent number: 9779982
    Abstract: This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device, a dielectric layer, and a first semiconductor layer; b) providing a second structure successively including a substrate, an active layer, a dielectric layer, and a second semiconductor layer, the active layer being designed to form an electronic device; c) bonding the first and second structures by direct bonding between the first and second semiconductor layers so as to form a bonding interface; d) removing the substrate of the second structure so as to expose the active layer; e) introducing dopants into the first and second semiconductor layers so as to form a ground plane.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 3, 2017
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine Batude, Laurent Brunet, Claire Fenouillet-Beranger, Frank Fournel
  • Patent number: 9761607
    Abstract: A method for producing a microelectronic device is provided, including forming on an insulating layer of a semi-conductor on insulator type substrate, a first semi-conductor block covered with a first strain zone configured to induce a compressive strain in the first block and a second semi-conductor block covered with a second strain zone configured to induce a tensile strain in the second block, the first block and the second block each being formed of a lower region based on amorphous semi-conductor material, covered with an upper region of crystalline semi-conductor material in contact with one of the strain zones; and recrystallizing the lower region of the first and second blocks while using the upper region of crystalline material as starting zone for a recrystallization front.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 12, 2017
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Shay Reboh, Perrine Batude, Sylvain Maitrejean, Frederic Mazen
  • Publication number: 20170221767
    Abstract: A method is provided for forming a transistor from a stack including the following successive layers: an electrically insulating layer, an active zone including at least one semiconductor layer, and a gate, sides of which are configured to be covered by at least one spacer, the method including: a phase of forming lateral cavities; and forming a raised drain and a raised source that fill the lateral cavities by growing the semiconductor layer via epitaxy, the forming of the lateral cavities includes, after a step of partially removing the semiconductor layer: forming a sacrificial layer, partially removing the sacrificial layer; forming spacers against the sides of the gate resting on a residual sacrificial layer; and totally removing the residual sacrificial layer in order to form the lateral cavities.
    Type: Application
    Filed: February 1, 2017
    Publication date: August 3, 2017
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Laurent BRUNET, Perrine BATUDE
  • Publication number: 20170178950
    Abstract: This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device, a dielectric layer, and a first semiconductor layer; b) providing a second structure successively including a substrate, an active layer, a dielectric layer, and a second semiconductor layer, the active layer being designed to form an electronic device; c) bonding the first and second structures by direct bonding between the first and second semiconductor layers so as to form a bonding interface; d) removing the substrate of the second structure so as to expose the active layer; e) introducing dopants into the first and second semiconductor layers so as to form a ground plane.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 22, 2017
    Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine BATUDE, Laurent BRUNET, Claire FENOUILLET-BERANGER, Frank FOURNEL