Patents by Inventor Perrine Batude

Perrine Batude has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170178950
    Abstract: This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device, a dielectric layer, and a first semiconductor layer; b) providing a second structure successively including a substrate, an active layer, a dielectric layer, and a second semiconductor layer, the active layer being designed to form an electronic device; c) bonding the first and second structures by direct bonding between the first and second semiconductor layers so as to form a bonding interface; d) removing the substrate of the second structure so as to expose the active layer; e) introducing dopants into the first and second semiconductor layers so as to form a ground plane.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 22, 2017
    Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine BATUDE, Laurent BRUNET, Claire FENOUILLET-BERANGER, Frank FOURNEL
  • Patent number: 9502566
    Abstract: The invention concerns a method for producing a transistor. The gate of the transistor is produced after having produced source and drain electrodes of the transistor. From a substrate having a stack of layers comprising at least two surface layers with a first layer of a first semiconductor material intended to produce a conduction channel of the transistor, and a second layer of a second semiconductor material situated on the first layer and intended to at least partly produce the source and drain electrodes of the transistor, the formation of a mask defining a cavity of a gate pattern and the creation of lateral recesses at the periphery of the gate pattern in the second layer and under the mask by an isotropic etching of the second material, and in that it comprises a filling of the lateral recesses with a dielectric material so as to form gate spacers therein.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: November 22, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire Fenouillet-Beranger, Perrine Batude
  • Publication number: 20160300927
    Abstract: Method including the steps consisting in: forming source and drain semiconductor blocks comprising a first layer based on a first crystalline semiconductor material surmounted by a second layer (16) based on a second crystalline semiconductor material different from the first semiconductor material, making amorphous and selectively doping the second layer (16) by means of one or more implantation(s), carrying out a recrystallisation of the second layer and an activation of dopants by means of at least one thermal annealing.
    Type: Application
    Filed: April 6, 2016
    Publication date: October 13, 2016
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Shay REBOH, Perrine BATUDE, Frederic MAZEN, Benoit SKLENARD
  • Patent number: 9379213
    Abstract: Method for fabricating a transistor comprising the steps consisting of: forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone, forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor, removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers, forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: June 28, 2016
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMICROELECTRONICS SA
    Inventors: Perrine Batude, Jean-Michel Hartmann, Benoit Sklenard, Maud Vinet
  • Publication number: 20160181155
    Abstract: Method of making an integrated circuit, comprising at least the following steps: a) form a first semiconducting or conducting element, covered with a first insulating layer on which there is a second semiconducting or conducting element, covered with a second insulating layer; b) form an opening passing through at least the second insulating layer, exposing a portion of the second element and opening up at least partly on the second element or adjacent to the second element; c) form a spacer located at the second element and comprising at least one dielectric material located at least between the second element and the opening; d) prolong the opening through the first insulating layer as far as the first element; and e) fill the opening with at least one conducting material, so as to form a contact. FIG 1G.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 23, 2016
    Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives
    Inventors: Fabien DEPRAT, Perrine BATUDE, Yves MORAND, Heimanu NIEBOJEWKSI, Nicolas POSSEME
  • Patent number: 9343375
    Abstract: Method of manufacturing a transistor on a layer made of a first crystalline semiconducting material to make a channel, deposited on a dielectric layer, the method including the following steps: epitaxial growth of zones made of a second semiconducting material on the layer made of a first crystalline semiconducting material, so as to form source and drain blocks with the layer made of a first crystalline semiconducting material on each side of the channel, the second semiconducting material having a lattice parameter different from that of the first semiconducting material, in-depth amorphization of part of zones made of a second semiconducting material so as to keep only one layer of second crystalline semiconducting material on the surface of the source and drain blocks, and amorphization of zones of the layer made of a first semiconducting material located under zones made of a second semiconducting material, recrystallization of the source and drain blocks such that the second semiconducting material i
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: May 17, 2016
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Perrine Batude, Frederic Mazen, Shay Reboh, Benoit Sklenard
  • Patent number: 9246006
    Abstract: A method for manufacturing a transistor is provided, including amorphization and doping, by one or more localized implantations, of given regions of source and drain blocks based on crystalline semi-conductor material disposed on an insulating layer of a semi-conductor on insulator substrate, the implantations being carried out so as to conserve at a surface of said blocks zones of crystalline semi-conductor material on regions of amorphous semi-conductor material; and recrystallization of at least one portion of said given regions.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: January 26, 2016
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMICROELECTRONICS SA
    Inventors: Perrine Batude, Frederic Mazen, Benoit Sklenard, Shay Reboh
  • Publication number: 20160020153
    Abstract: Method of manufacturing a transistor on a layer made of a first crystalline semiconducting material to make a channel, deposited on a dielectric layer, the method including the following steps: epitaxial growth of zones made of a second semiconducting material on the layer made of a first crystalline semiconducting material, so as to form source and drain blocks with the layer made of a first crystalline semiconducting material on each side of the channel, the second semiconducting material having a lattice parameter different from that of the first semiconducting material, in-depth amorphisation of part of zones made of a second semiconducting material so as to keep only one layer of second crystalline semiconducting material on the surface of the source and drain blocks, and amorphisation of zones of the layer made of a first semiconducting material located under zones made of a second semiconducting material, recrystallisation of the source and drain blocks such that the second semiconducting material i
    Type: Application
    Filed: July 17, 2015
    Publication date: January 21, 2016
    Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives
    Inventors: Perrine BATUDE, Frederic MAZEN, Shay REBOH, Benoit SKLENARD
  • Publication number: 20150179665
    Abstract: Method for producing a microelectronic device comprising: a) the formation on an insulating layer of a semi-conductor on insulator type substrate, a first semi-conductor block covered with a first strain zone adapted to induce a compressive strain in said first block and a second semi-conductor block covered with a second strain zone adapted to induce a tensile strain in said second block, the first block and the second block each being formed of a lower region based on amorphous semi-conductor material, covered with an upper region of crystalline semi-conductor material in contact with one of said strain zones, b) the re-crystallization of said lower region of said first block and of said second block while using said upper region of crystalline material as starting zone for a recrystallization front.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 25, 2015
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Shay REBOH, Perrine BATUDE, Sylvain MAITREJEAN, Frederic MAZEN
  • Patent number: 9018078
    Abstract: A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: April 28, 2015
    Assignees: STMicroelectronics SA, Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Benoit Sklenard, Perrine Batude
  • Publication number: 20150084095
    Abstract: The invention concerns a method for producing a transistor. The gate of the transistor is produced after having produced source and drain electrodes of the transistor. From a substrate having a stack of layers comprising at least two surface layers with a first layer of a first semiconductor material intended to produce a conduction channel of the transistor, and a second layer of a second semiconductor material situated on the first layer and intended to at least partly produce the source and drain electrodes of the transistor, the formation of a mask defining a cavity of a gate pattern and the creation of lateral recesses at the periphery of the gate pattern in the second layer and under the mask by an isotropic etching of the second material, and in that it comprises a filling of the lateral recesses with a dielectric material so as to form gate spacers therein.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 26, 2015
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Claire FENOUILLET-BERANGER, Perrine Batude
  • Publication number: 20150044841
    Abstract: Method for fabricating a transistor comprising the steps consisting of: forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone, forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor, removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers, forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.
    Type: Application
    Filed: August 4, 2014
    Publication date: February 12, 2015
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT, STMICROELECTRONICS SA
    Inventors: Perrine BATUDE, Jean-Michel HARTMANN, Benoit SKLENARD, Maud VINET
  • Publication number: 20150044828
    Abstract: A Method for manufacturing a transistor comprising: a) amorphization and doping, by means of one or more localised implantation(s), of given regions of source and drain blocks based on crystalline semi-conductor material lying on an insulating layer of a semi-conductor on insulator substrate, the implantation(s) being carried out so as to conserve at the surface of said blocks zones of crystalline semi-conductor material on the regions of amorphous semi-conductor material, b) recrystallization of at least one portion of said given regions.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 12, 2015
    Applicants: COMMISARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT, STMICROELECTRONICS SA
    Inventors: Perrine BATUDE, Frederic Mazen, Benoit Sklenard
  • Patent number: 8853785
    Abstract: An integrated circuit including at least: a first MOS transistor; a second MOS transistor, arranged on the first MOS transistor, the second MOS transistor including a channel region in at least one semiconductor layer including two approximately parallel primary faces; a portion of at least one electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged at least between the portion of the electrically conductive material and the channel region of the second transistor; and a section of the channel region of the second transistor in a plane parallel to the two primary faces of the semiconductor layer is included in a section of the portion of the electrically conductive material projected in said plane.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: October 7, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Emmanuel Augendre, Maud Vinet, Laurent Clavelier, Perrine Batude
  • Patent number: 8722471
    Abstract: A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: May 13, 2014
    Assignees: STMicroelectronics S.A., Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Perrine Batude, Yves Morand
  • Publication number: 20130203248
    Abstract: A method for producing an integrated circuit, including, in this order: a) producing at least one MOS electronic circuit and/or at least one level of electrical interconnections on a substrate; b) uniformly implantating dopants in at least a portion of a layer of crystalline semiconductor; c) thermally activating the dopants implanted in the portion of the crystalline semiconductor layer; d) rigidly connecting the crystalline semiconductor layer to the substrate; and e) producing at least one junctionless depletion-mode FET device including a part of the portion of the crystalline semiconductor layer.
    Type: Application
    Filed: June 6, 2011
    Publication date: August 8, 2013
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Thomas Ernst, Marie-Anne Jaud, Perrine Batude
  • Patent number: 8183630
    Abstract: A microelectronic device including: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor including a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by an insulating zone, and said insulating zone being constituted of several different dielectric materials include a first dielectric material and a second dielectric material.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: May 22, 2012
    Assignee: Commissariat A L'Energie Atomique
    Inventors: Perrine Batude, Laurent Clavelier, Marie-Anne Jaud, Olivier Thomas, Maud Vinet
  • Patent number: 8013399
    Abstract: A static random access memory cell which, on a substrate surmounted by a stack of layers, including: a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor are connected to a word line and are arranged between a first bit line and a first storage node and a second bit line and a second storage node, respectively; and a second plurality of transistors forming a flip-flop and situated at least one other level of the stack, beneath said given level, wherein the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by an insulating region provided to enable coupling of said gate electrode and said channel region.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: September 6, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Olivier Thomas, Perrine Batude, Arnaud Pouydebasque, Maud Vinet
  • Publication number: 20110147849
    Abstract: An integrated circuit including: a first transistor; a second transistor, arranged on the first transistor, whereof a channel region is formed in a semiconductor layer including two approximately parallel primary faces; a portion of an electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged between the portion of the electrically conductive material and the channel region of the second transistor; and in which the section of the channel region of the second transistor is included in the section of the portion of the electrically conductive material, and the channel region of the second transistor is arranged between the portion of the electrically conductive material and a gate of the second transistor.
    Type: Application
    Filed: August 25, 2010
    Publication date: June 23, 2011
    Applicant: COMMISS. A L'ENERGIE ATOM. ET AUX ENERG. ALTERNA.
    Inventors: Emmanuel AUGENDRE, Maud Vinet, Laurent Clavelier, Perrine Batude
  • Publication number: 20090294861
    Abstract: A non-volatile random access memory cell which, on a substrate surmounted by a stack of layers, comprises: a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor, which are arranged between a first bit line and a first storage node, and between a second bit line and a second storage node, respectively, the first access transistor and the second access transistor having a gate connected to a word line, a second plurality of transistors forming a flip-flop and situated at, at least one other level of the stack, beneath said given level, the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by means of an insulating region provided to enable coupling of said gate electrode and said channel region.
    Type: Application
    Filed: May 15, 2009
    Publication date: December 3, 2009
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Olivier THOMAS, Perrine Batude, Arnaud Pouydebasque, Maud Vinet