Abstract: Methods and systems of heating a substrate in a vacuum deposition process include a resistive heater having a resistive heating element. Radiative heat emitted from the resistive heating element has a wavelength in a mid-infrared band from 5 ?m to 40 ?m that corresponds to a phonon absorption band of the substrate. The substrate comprises a wide bandgap semiconducting material and has an uncoated surface and a deposition surface opposite the uncoated surface. The resistive heater and the substrate are positioned in a vacuum deposition chamber. The uncoated surface of the substrate is spaced apart from and faces the resistive heater.

Abstract: Various forms of Mga(Six(GeySn1-y)1-x)Ob are disclosed. In some aspects, an epitaxial layer comprises single crystal Mga(Six(GeySn1-y)1-x)Ob, wherein 1.5?a?2.5, 3?b?5, 0?x?1, and 0?y?1; wherein the single crystal Mga(Six(GeySn1-y)1-x)Ob has a crystal symmetry compatible with a substrate or an underlying layer on which the single crystal Mga(Six(GeySn1-y)1-x)Ob is grown. In some aspects, a semiconductor structure includes an epitaxial layer comprising single crystal Mga(Six(GeySn1-y)1-x)Ob, wherein 1.5?a?2.5, 3?b?5, 0?x?1, and 0?y?1; The semiconductor structure also includes a substrate or an underlying layer on which the single crystal Mga(Six(GeySn1-y)1-x)Ob is grown; wherein the single crystal Mga(Six(GeySn1-y)1-x)Ob has a crystal symmetry compatible with the substrate or the underlying layer.

Abstract: Methods of forming oxide-based semiconductor layers include rotating a substrate around a center axis of a substrate deposition plane; heating the substrate; and emitting materials from a plurality of material sources to form an oxide-based layer on the substrate. The material sources comprise a source of oxygen species and at least other two material sources. Each material source has i) an exit aperture with an exit aperture plane and ii) a predetermined material ejection spatial distribution from the exit aperture plane, the material ejection spatial distribution having a symmetry axis which intersects the substrate at a point offset from the center axis. The exit aperture is positioned to achieve a desired layer deposition uniformity for a desired layer growth rate of the oxide-based layer.

Abstract: In some embodiments, the techniques described herein relate to an epitaxial oxide transistor. The transistor can include: a substrate; a channel layer including a first epitaxial semiconductor layer on the substrate; a gate layer including a second epitaxial semiconductor layer on the first epitaxial semiconductor layer; a source electrode and a drain electrode coupled to the channel layer; and a gate electrode coupled to the gate layer. The first epitaxial semiconductor layer can include a first polar oxide material and the second epitaxial semiconductor layer can include a second polar oxide material. The first polar oxide material and the second polar oxide material can include cation-polar surfaces oriented towards or away from the substrate, and the second polar oxide material can include a wider bandgap than the first polar oxide material.

Abstract: Methods and systems of heating a substrate in a vacuum deposition process include a resistive heater having a resistive heating element. Radiative heat emitted from the resistive heating element has a wavelength in a mid-infrared band from 5 ?m to 40 ?m that corresponds to a phonon absorption band of the substrate. The substrate comprises a wide bandgap semiconducting material and has an uncoated surface and a deposition surface opposite the uncoated surface. The resistive heater and the substrate are positioned in a vacuum deposition chamber. The uncoated surface of the substrate is spaced apart from and faces the resistive heater. The uncoated surface of the substrate is directly heated by absorbing the radiative heat.

Abstract: In some embodiments, a semiconductor structure includes: a first epitaxial oxide semiconductor layer; a metal layer; and a contact layer adjacent to the metal layer, and between the first epitaxial oxide semiconductor layer and the metal layer. The contact layer can include an epitaxial oxide semiconductor material. The contact layer can also include a region comprising a gradient in a composition of the epitaxial oxide semiconductor material adjacent to the metal layer, or a gradient in a strain of the epitaxial oxide semiconductor material over a region adjacent to the metal layer.

Abstract: Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

Abstract: Various forms of MgxGe1-xO2-x are disclosed, where the MgxGe1-xO2-x are epitaxial layers formed on a substrate comprising a substantially single crystal substrate material. The epitaxial layer of MgxGe1-xO2-x has a crystal symmetry compatible with the substrate material. Semiconductor structures and devices comprising the epitaxial layer of MgxGe1-xO2-x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices. Also disclosed is single crystal MgxGe1-xO2-x, with x having a value of 0?x<1. The single crystal MgxGe1-xO2-x may comprise a dopant chosen from Ga, Al, Li+, N3+. The single crystal MgxGe1-xO2-x may comprise a p-type conductivity.

Abstract: A multilayered semiconductor device including a substrate including n-type or p-type doped silicon carbide (SiC), an epitaxial oxide layer above the substrate, and a metal layer above the epitaxial oxide layer. In some cases, the epitaxial oxide layer includes n-type conductivity and the substrate is p-type doped, and the substrate and the epitaxial oxide layer form a p/n junction. In some cases, the device can further include an epitaxial transition layer between the substrate and the epitaxial oxide layer, where the epitaxial transition layer includes an n-type doping density that is at least an order of magnitude greater than an n-type doping density of the epitaxial oxide layer. In some cases, the substrate can be a composite substrate including a surface layer including single crystal SiC on a polycrystalline SiC layer. In some cases, a second metal layer is in contact with the substrate.

Abstract: A multilayered semiconductor diode device can include a substrate including silicon carbide (SiC) with an epitaxial drift layer including a first semiconductor oxide material above the SiC substrate with respect to a growth direction. The multilayered semiconductor diode device can further include a polar nitride layer including a polar semiconductor nitride material above the epitaxial drift layer with respect to the growth direction, and a metal layer above the polar nitride layer with respect to the growth direction.

Abstract: In some embodiments, the techniques described herein relate to a multilayered semiconductor diode device including: a substrate including silicon carbide (SiC); an epitaxial drift layer including a first semiconductor oxide material or SiC on the substrate; an epitaxial channel layer including a second semiconductor oxide material on the epitaxial drift layer; and a metal layer above the epitaxial drift layer to form a Schottky barrier junction. The epitaxial channel layer and the Schottky metal layer form a mesa structure contacting a sidewall layer. In some embodiments, a method of forming a multilayered semiconductor diode device includes: providing a substrate including silicon carbide (SiC); forming an epitaxial drift layer; forming an epitaxial channel layer; forming a metal layer to form a Schottky barrier junction; etching the epitaxial channel layer and the metal layer to form a mesa structure; and forming a sidewall layer contacting a wall of the mesa structure.

Abstract: A multilayered semiconductor device includes a substrate comprising silicon carbide (SiC) and an epitaxial transition layer comprising a first epitaxial oxide material or SiC on the substrate. One or more epitaxial active regions comprising one or more second epitaxial oxide materials are formed on the epitaxial transition layer, and a metal layer is formed above the one or more epitaxial active regions, the metal layer comprising one or more electrical contacts. The multilayered semiconductor device comprises one of a metal-oxide field-effect transistor, a vertical conduction metal-oxide field-effect transistor, a lateral field-effect transistor, a metal-semiconductor field-effect transistor, a bipolar junction transistor, a junction field-effect transistor, a metal-insulator-semiconductor device, a PN device, a PNP device, an NPN device, or an insulated-gate bipolar transistor.

Abstract: An integrated circuit is formed on a substrate of single crystal silicon carbide or a composite substrate with a top layer of single crystal silicon carbide (and optionally a bottom layer of polycrystalline silicon carbide or a sacrificial material). An active layer (which may be an oxide such as Ga2O3) is epitaxially grown on the substrate, and an active device is formed in the active layer. A handle is bonded to a top surface of the active device. At least a portion of the substrate is removed from a backside of the integrated circuit.

Abstract: A multilayered semiconductor device including a substrate including n-type or p-type doped silicon carbide (SiC), an epitaxial oxide layer above the substrate, and a metal layer above the epitaxial oxide layer. In some cases, the epitaxial oxide layer includes n-type conductivity and the substrate is p-type doped, and the substrate and the epitaxial oxide layer form a p/n junction. In some cases, the device can further include an epitaxial transition layer between the substrate and the epitaxial oxide layer, where the epitaxial transition layer includes an n-type doping density that is at least an order of magnitude greater than an n-type doping density of the epitaxial oxide layer. In some cases, the substrate can be a composite substrate including a surface layer including single crystal SiC on a polycrystalline SiC layer. In some cases, a second metal layer is in contact with the substrate.

Abstract: A semiconductor structure includes a superlattice with two or more unit cells, wherein each of the unit cells includes: a first epitaxial layer including NiO; and a second epitaxial layer including a second epitaxial oxide material. In some cases, the semiconductor structure can include: a first region including p-type conductivity, wherein the first region includes the superlattice; a second region including an epitaxial oxide material; and a third region including an epitaxial oxide material, wherein the second region is located between the first region and the third region along a growth direction.

Abstract: In embodiments, methods of configuring a molecular beam epitaxy system include providing a rotation mechanism configured to rotate a substrate deposition plane of a substrate around a center axis of the substrate deposition plane. A positioning mechanism is provided, being configured to allow the substrate deposition plane and an exit aperture of at least one material source in a plurality of material sources to be adjusted in position relative to each other between production runs. The at least one material source has a predetermined material ejection spatial distribution with a symmetry axis that intersects the substrate at a point offset from the center axis. A size of a reaction chamber, that houses the rotation mechanism and the plurality of material sources, is scaled based on the orthogonal distance and the lateral distance in relationship to a radius of the substrate.

Abstract: The techniques described herein relate to a semiconductor structure including: a substrate, or a single crystal growth surface, including single crystal 4H-SiC(0001); a buffer layer on the single crystal growth surface; and an epitaxial oxide layer on the buffer layer. The buffer layer can include a crystal symmetry type that is compatible with the single crystal 4H-SiC(0001). The epitaxial oxide layer can include single crystal (AlxGa1-x)2O3 with a monoclinic or corundum crystal symmetry, and where 0?x?1.

Abstract: A transistor can include a substrate, an epitaxial oxide layer on the substrate, and a gate layer. The substrate can include a first crystalline material. The epitaxial oxide layer can include a second oxide material including: Li and one of Ni, Al, Ga, Mg, Zn and Ge; or Ni and one of Li, Al, Ga, Mg, Zn and Ge; or Mg and one of Ni, Al, Ga, and Ge; or Zn and one of Ni, Al, Ga, and Ge. The gate layer can include a third oxide material. A bandgap of the third oxide material of the gate can be wider than a bandgap of the second oxide material of the epitaxial oxide layer. The transistor can also include a source electrical contact coupled to the epitaxial oxide layer, a drain electrical contact coupled to the epitaxial oxide layer, and a first gate electrical contact coupled to the gate layer.

Abstract: In some embodiments, a semiconductor structure includes: a first epitaxial oxide semiconductor layer; a metal layer; and a contact layer adjacent to the metal layer, and between the first epitaxial oxide semiconductor layer and the metal layer. The contact layer can include an epitaxial oxide semiconductor material. The contact layer can also include a region comprising a gradient in a composition of the epitaxial oxide semiconductor material adjacent to the metal layer, or a gradient in a strain of the epitaxial oxide semiconductor material over a region adjacent to the metal layer.

Abstract: The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate comprising a first oxide material; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.