Abstract: An amplifier for converting a single-ended input signal to a differential output signal. The amplifier comprises a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor, configured in common-source or common-emitter mode, receives the single-ended input signal and generates a first part of the differential output signal. The second transistor, also configured in common-source or common-emitter mode, generates a second part of the differential output signal. The third and fourth transistors are capacitively cross-coupled. The amplifier further comprises inductive degeneration such that a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor.

Abstract: A local oscillator signal generation circuit (150) for generating quadrature-related local oscillator signals comprises a source signal generator (153) arranged to generate a differential-mode source signal, a buffer stage (158) coupled to an output (156) of the source signal generator (153) and arranged to buffer the differential-mode source signal, and a quadrature generation stage (170) coupled to an output (168) of the buffer stage (158) and arranged to generate an in-phase local oscillator signal and a quadrature local oscillator signal from the buffered differential-mode source signal. The buffer stage (158) comprises a primary differential amplifier (159) having an input (162) coupled to an input (157) of the buffer stage (158), and a secondary differential amplifier (160) having an input (164) coupled to an output (163) of the primary differential amplifier (159) and an output (165) coupled to the output (168) of the buffer stage (158).

Abstract: A resistor network comprises one or more switched resistor branches. Each switched resistor branch comprises a first resistor connected in series with a first switch, wherein a first terminal of the first resistor is connected to the input terminal of the resistor network, a second terminal of the first resistor is connected to a first terminal of the first switch forming a middle node, and a second terminal of the first switch is connected to the output terminal of the resistor network. Each switched resistor branch further comprises a second resistor connected in series with a second switch, wherein the series connected second resistor and second switch is connected between the middle node and a third terminal of the one or more switched resistor branches. The resistor network further comprises a third resistor connected between the input and output terminals of the resistor network.

Abstract: A resistor network comprises one or more switched resistor branches. Each switched resistor branch comprises a first resistor connected in series with a first switch, wherein a first terminal of the first resistor is connected to the input terminal of the resistor network, a second terminal of the first resistor is connected to a first terminal of the first switch forming a middle node, and a second terminal of the first switch is connected to the output terminal of the resistor network. Each switched resistor branch further comprises a second resistor connected in series with a second switch, wherein the series connected second resistor and second switch is connected between the middle node and a third terminal of the one or more switched resistor branches. The resistor network further comprises a third resistor connected between the input and output terminals of the resistor network.

Abstract: The method and apparatus described herein address problems associated with conventional wireless receivers configured for intra-band carrier aggregation. The disclosed solution applies the received signal to a single front-end amplifier, which may comprise a low-noise amplifier, and divides the amplified signal into two or more processing paths, where each path is associated with a different local oscillator frequency corresponding to a different reception band. To compensate for the impact of the additional processing paths on the amplifier performance, a negative resistor unit applies a negative resistance to the output of the front-end amplifier when two or more processing paths are active.

Abstract: The method and apparatus disclosed herein reduces the power consumption of a wireless transceiver by reducing the power consumption associated with the corresponding wireless receiver. Generally, a power mode selection unit enables or disables a low power mode based on a dynamic range requirement for the receiver. More particularly, when the dynamic range requirement is less than or equal to a threshold, the power mode selection unit lowers the transconductance of an RF front-end amplifier in the receiver and enables a negative resistance at an output of the RF front-end amplifier. When enabled, the negative resistance compensates for the gain lost by lowering the transconductance of the RF front-end amplifier, which enables the front-end gain associated with the low-power mode to be maintained relative front-end gain associated with the normal mode.

Abstract: An integrated circuit for a radio receiver comprising a radio-frequency amplifier and a radio-frequency filter is described. The amplifier receives radio-frequency signals from an antenna, the filter is connected to the amplifier output, and the output of the filter is provided to a processing stage of the receiver. The amplifier comprises an amplifying stage controlled by a radio-frequency input signal and a signal fed back from the filter. The amplifier input impedance is substantially matched to the antenna impedance at a frequency band of interest. The signal fed back from the filter providing attenuation of signals outside the frequency band of interest at the amplifier input. The filter comprises one or more filter components.

Abstract: The method and apparatus described herein address problems associated with conventional wireless receivers configured for intra-band carrier aggregation. The disclosed solution applies the received signal to a single front-end amplifier, which may comprise a low-noise amplifier, and divides the amplified signal into two or more processing paths, where each path is associated with a different local oscillator frequency corresponding to a different reception band. To compensate for the impact of the additional processing paths on the amplifier performance, a negative resistor unit applies a negative resistance to the output of the front-end amplifier when two or more processing paths are active.

Abstract: The method and apparatus disclosed herein reduces the power consumption of a wireless transceiver by reducing the power consumption associated with the corresponding wireless receiver. Generally, a power mode selection unit enables or disables a low power mode based on a dynamic range requirement for the receiver. More particularly, when the dynamic range requirement is less than or equal to a threshold, the power mode selection unit lowers the transconductance of an RF front-end amplifier in the receiver and enables a negative resistance at an output of the RF front-end amplifier. When enabled, the negative resistance compensates for the gain lost by lowering the transconductance of the RF front-end amplifier, which enables the front-end gain associated with the low-power mode to be maintained relative front-end gain associated with the normal mode.

Abstract: An integrated circuit for a radio receiver comprising a radio-frequency amplifier and a radio-frequency filter is described. The amplifier receives radio-frequency signals from an antenna, the filter is connected to the amplifier output, and the output of the filter is provided to a processing stage of the receiver. The amplifier comprises an amplifying stage controlled by a radio-frequency input signal and a signal fed back from the filter. The amplifier input impedance is substantially matched to the antenna impedance at a frequency band of interest. The signal fed back from the filter providing attenuation of signals outside the frequency band of interest at the amplifier input. The filter comprises one or more filter components.

Abstract: A transconductor input circuit for a down converting quadrature mixer stage of a direct-conversion receiver comprises a pair of common-gate input transistors whose source electrodes are coupled to a differential radio frequency (RF) input signal outputted from an interstage RF filter. The transconductor circuit further comprises a pair of equally-sized biasing transistors for biasing the pair of common-gate input transistors. Source electrodes of the biasing transistors are coupled to the source electrodes of the transistors to sense the differential radio frequency input signal for canceling intermodulation distortion.

Abstract: A transconductor input circuit for a down converting quadrature mixer stage of a direct-conversion receiver comprises a pair of common-gate input transistors whose source electrodes are coupled to a differential radio frequency (RF) input signal outputted from an interstage RF filter. The transconductor circuit further comprises a pair of equally-sized biasing transistors for biasing the pair of common-gate input transistors. Source electrodes of the biasing transistors are coupled to the source electrodes of the transistors to sense the differential radio frequency input signal for canceling intermodulation distortion.

Abstract: A transconductor circuit includes a first input device M1 and a second input device M2 each having a control terminal coupled to a radio frequency input signal, and a bias setting device MB having a control terminal coupled to the radio frequency input signal and an output coupled to the control terminal of each of said M1 and M2. MB is partitioned into two equal sized bias setting devices MB1 and MB2. In the preferred embodiment MB1 and MB2 are coupled to the control terminals of M1 and M2 for establishing a bias voltage at the control terminals of M1 and M2. The circuit is shown to substantially cancel second-order intermodulation distortion and to enhance a second order intercept point.

Abstract: A resonant load circuit is disposed in an integrated circuit, where the resonant load circuit includes an integrated inductance in parallel with an integrated capacitance, and further includes a first integrated resistance Rs in series with one of the inductance and capacitance, preferably in series with the inductance, and a second integrated resistance Rp in parallel with the inductance and capacitance. The first and second integrated resistances have values selected for reducing an amount of resonant load circuit Q over a plurality of instances of the integrated circuit. In a preferred, but non-limiting, embodiment the resonant load circuit forms a load in an RF low noise amplifier, such as a balanced inductively degenerated common source low noise amplifier (LNA).

Abstract: A transconductor circuit includes a first input device M1 and a second input device M2 each having a control terminal coupled to a radio frequency input signal, and a bias setting device MB having a control terminal coupled to the radio frequency input signal and an output coupled to the control terminal of each of said M1 and M2. MB is partitioned into two equal sized bias setting devices MB1 and MB2. In the preferred embodiment MB1 and MB2 are coupled to the control terminals of M1 and M2 for establishing a bias voltage at the control terminals of M1 and M2. The circuit is shown to substantially cancel second-order intermodulation distortion and to enhance a second order intercept point.

Abstract: A resonant load circuit is disposed in an integrated circuit, where the resonant load circuit includes an integrated inductance in parallel with an integrated capacitance, and further includes a first integrated resistance Rs in series with one of the inductance and capacitance, preferably in series with the inductance, and a second integrated resistance Rp in parallel with the inductance and capacitance. The first and second integrated resistances have values selected for reducing an amount of resonant load circuit Q over a plurality of instances of the integrated circuit. In a preferred, but non-limiting, embodiment the resonant load circuit forms a load in an RF low noise amplifier, such as a balanced inductively degenerated common source low noise amplifier (LNA).