Patents by Inventor Pete Sivonen

Pete Sivonen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8548410
    Abstract: The method and apparatus described herein address problems associated with conventional wireless receivers configured for intra-band carrier aggregation. The disclosed solution applies the received signal to a single front-end amplifier, which may comprise a low-noise amplifier, and divides the amplified signal into two or more processing paths, where each path is associated with a different local oscillator frequency corresponding to a different reception band. To compensate for the impact of the additional processing paths on the amplifier performance, a negative resistor unit applies a negative resistance to the output of the front-end amplifier when two or more processing paths are active.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: October 1, 2013
    Assignee: St-Ericsson SA
    Inventors: Jarkko Jussila, Pete Sivonen
  • Patent number: 8526907
    Abstract: The method and apparatus disclosed herein reduces the power consumption of a wireless transceiver by reducing the power consumption associated with the corresponding wireless receiver. Generally, a power mode selection unit enables or disables a low power mode based on a dynamic range requirement for the receiver. More particularly, when the dynamic range requirement is less than or equal to a threshold, the power mode selection unit lowers the transconductance of an RF front-end amplifier in the receiver and enables a negative resistance at an output of the RF front-end amplifier. When enabled, the negative resistance compensates for the gain lost by lowering the transconductance of the RF front-end amplifier, which enables the front-end gain associated with the low-power mode to be maintained relative front-end gain associated with the normal mode.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: September 3, 2013
    Assignee: ST-Ericsson SA
    Inventors: Pete Sivonen, Jarkko Jussila
  • Patent number: 8503963
    Abstract: An integrated circuit for a radio receiver comprising a radio-frequency amplifier and a radio-frequency filter is described. The amplifier receives radio-frequency signals from an antenna, the filter is connected to the amplifier output, and the output of the filter is provided to a processing stage of the receiver. The amplifier comprises an amplifying stage controlled by a radio-frequency input signal and a signal fed back from the filter. The amplifier input impedance is substantially matched to the antenna impedance at a frequency band of interest. The signal fed back from the filter providing attenuation of signals outside the frequency band of interest at the amplifier input. The filter comprises one or more filter components.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: August 6, 2013
    Assignee: St-Ericsson SA
    Inventors: Pete Sivonen, Jonne Riekki, Jouni Kaukovuori, Sami Vilhonen, Jarkko Jussila
  • Publication number: 20130137386
    Abstract: The method and apparatus disclosed herein reduces the power consumption of a wireless transceiver by reducing the power consumption associated with the corresponding wireless receiver. Generally, a power mode selection unit enables or disables a low power mode based on a dynamic range requirement for the receiver. More particularly, when the dynamic range requirement is less than or equal to a threshold, the power mode selection unit lowers the transconductance of an RF front-end amplifier in the receiver and enables a negative resistance at an output of the RF front-end amplifier. When enabled, the negative resistance compensates for the gain lost by lowering the transconductance of the RF front-end amplifier, which enables the front-end gain associated with the low-power mode to be maintained relative front-end gain associated with the normal mode.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Inventors: Pete Sivonen, Jarkko Jussila
  • Publication number: 20130136211
    Abstract: The method and apparatus described herein address problems associated with conventional wireless receivers configured for intra-band carrier aggregation. The disclosed solution applies the received signal to a single front-end amplifier, which may comprise a low-noise amplifier, and divides the amplified signal into two or more processing paths, where each path is associated with a different local oscillator frequency corresponding to a different reception band. To compensate for the impact of the additional processing paths on the amplifier performance, a negative resistor unit applies a negative resistance to the output of the front-end amplifier when two or more processing paths are active.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Inventors: Jarkko Jussila, Pete Sivonen
  • Publication number: 20120171980
    Abstract: An integrated circuit for a radio receiver comprising a radio-frequency amplifier and a radio-frequency filter is described. The amplifier receives radio-frequency signals from an antenna, the filter is connected to the amplifier output, and the output of the filter is provided to a processing stage of the receiver. The amplifier comprises an amplifying stage controlled by a radio-frequency input signal and a signal fed back from the filter. The amplifier input impedance is substantially matched to the antenna impedance at a frequency band of interest. The signal fed back from the filter providing attenuation of signals outside the frequency band of interest at the amplifier input. The filter comprises one or more filter components.
    Type: Application
    Filed: June 30, 2011
    Publication date: July 5, 2012
    Applicant: ST-Ericsson SA
    Inventors: Pete Sivonen, Jonne Riekki, Jouni Kaukovuori, Sami Vilhonen, Jarkko Jussila
  • Patent number: 7774019
    Abstract: A transconductor input circuit for a down converting quadrature mixer stage of a direct-conversion receiver comprises a pair of common-gate input transistors whose source electrodes are coupled to a differential radio frequency (RF) input signal outputted from an interstage RF filter. The transconductor circuit further comprises a pair of equally-sized biasing transistors for biasing the pair of common-gate input transistors. Source electrodes of the biasing transistors are coupled to the source electrodes of the transistors to sense the differential radio frequency input signal for canceling intermodulation distortion.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: August 10, 2010
    Assignee: Nokia Corporation
    Inventors: Pete Sivonen, Ari Vilander
  • Publication number: 20080261553
    Abstract: A transconductor input circuit for a down converting quadrature mixer stage of a direct-conversion receiver comprises a pair of common-gate input transistors whose source electrodes are coupled to a differential radio frequency (RF) input signal outputted from an interstage RF filter. The transconductor circuit further comprises a pair of equally-sized biasing transistors for biasing the pair of common-gate input transistors. Source electrodes of the biasing transistors are coupled to the source electrodes of the transistors to sense the differential radio frequency input signal for canceling intermodulation distortion.
    Type: Application
    Filed: July 18, 2007
    Publication date: October 23, 2008
    Inventors: Pete Sivonen, Ari Vilander
  • Patent number: 6992519
    Abstract: A transconductor circuit includes a first input device M1 and a second input device M2 each having a control terminal coupled to a radio frequency input signal, and a bias setting device MB having a control terminal coupled to the radio frequency input signal and an output coupled to the control terminal of each of said M1 and M2. MB is partitioned into two equal sized bias setting devices MB1 and MB2. In the preferred embodiment MB1 and MB2 are coupled to the control terminals of M1 and M2 for establishing a bias voltage at the control terminals of M1 and M2. The circuit is shown to substantially cancel second-order intermodulation distortion and to enhance a second order intercept point.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: January 31, 2006
    Assignee: Nokia Corporation
    Inventors: Ari Vilander, Pete Sivonen
  • Patent number: 6963247
    Abstract: A resonant load circuit is disposed in an integrated circuit, where the resonant load circuit includes an integrated inductance in parallel with an integrated capacitance, and further includes a first integrated resistance Rs in series with one of the inductance and capacitance, preferably in series with the inductance, and a second integrated resistance Rp in parallel with the inductance and capacitance. The first and second integrated resistances have values selected for reducing an amount of resonant load circuit Q over a plurality of instances of the integrated circuit. In a preferred, but non-limiting, embodiment the resonant load circuit forms a load in an RF low noise amplifier, such as a balanced inductively degenerated common source low noise amplifier (LNA).
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: November 8, 2005
    Assignee: Nokia Corporation
    Inventors: Pete Sivonen, Ari Vilander
  • Publication number: 20050174167
    Abstract: A transconductor circuit includes a first input device M1 and a second input device M2 each having a control terminal coupled to a radio frequency input signal, and a bias setting device MB having a control terminal coupled to the radio frequency input signal and an output coupled to the control terminal of each of said M1 and M2. MB is partitioned into two equal sized bias setting devices MB1 and MB2. In the preferred embodiment MB1 and MB2 are coupled to the control terminals of M1 and M2 for establishing a bias voltage at the control terminals of M1 and M2. The circuit is shown to substantially cancel second-order intermodulation distortion and to enhance a second order intercept point.
    Type: Application
    Filed: February 11, 2004
    Publication date: August 11, 2005
    Inventors: Ari Vilander, Pete Sivonen
  • Publication number: 20050110575
    Abstract: A resonant load circuit is disposed in an integrated circuit, where the resonant load circuit includes an integrated inductance in parallel with an integrated capacitance, and further includes a first integrated resistance Rs in series with one of the inductance and capacitance, preferably in series with the inductance, and a second integrated resistance Rp in parallel with the inductance and capacitance. The first and second integrated resistances have values selected for reducing an amount of resonant load circuit Q over a plurality of instances of the integrated circuit. In a preferred, but non-limiting, embodiment the resonant load circuit forms a load in an RF low noise amplifier, such as a balanced inductively degenerated common source low noise amplifier (LNA).
    Type: Application
    Filed: November 21, 2003
    Publication date: May 26, 2005
    Inventors: Pete Sivonen, Ari Vilander