Patents by Inventor Peter A. Burke
Peter A. Burke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050126913Abstract: Systems and methods are provided for the manipulation of a polarizable object with a pair of elongated nanoelectrodes using dielectrophoresis. The nanoelectrodes can be carbon nanotubes and are coupled with one or more time-varying voltage sources to create an electric field gradient in a gap between the nanotubes. The gradient induces the movement of a polarizable object in proximity with the field. The nanotube pair can be used to trap a single polarizable object in the gap. A method of fabricating a nanoelectrode dielectrophoretic system is also provided. Applications extend to self-fabricating nanoelectronics, nanomachines, nanochemistry and nanobiochemistry. A nanoelectrode dielectrophoretic system having an extended nanoelectrode for use in applications including the self-fabrication of a nanowire, as well as methods for fabricating the same, are also provided.Type: ApplicationFiled: February 27, 2004Publication date: June 16, 2005Inventors: Peter Burke, Shengdong Li, Lifeng Zheng
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Patent number: 6905909Abstract: A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.Type: GrantFiled: October 22, 2003Date of Patent: June 14, 2005Assignee: LSI Logic CorporationInventors: Hao Cui, Peter A. Burke, Wilbur G. Catabay
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Publication number: 20050090036Abstract: A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.Type: ApplicationFiled: October 22, 2003Publication date: April 28, 2005Inventors: Hao Cui, Peter Burke, Wilbur Catabay
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Publication number: 20050084415Abstract: A flash vaporizer (34) provides a constant flow of vaporized hydrogen peroxide or other antimicrobial compounds for rapidly sterilizing large enclosures (10), such as rooms or buildings. The vaporizer includes a heated block (50) which defines an interior bore or bores (70, 72, 74). The flowpath created by the bore or bores increases in cross sectional area as the hydrogen peroxide passes through the block to accommodate the increase in volume during the conversion from liquid to gas. The vapor is injected into dry air in a duct that circulates it to the large enclosure.Type: ApplicationFiled: September 14, 2004Publication date: April 21, 2005Inventors: Iain McVey, Francis Zelina, Aaron Hill, Peter Burke, Thaddeus Mielnik, Matthew Lawes, Gerald McDonnell, Kevin Williams
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Patent number: 6860802Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.Type: GrantFiled: June 30, 2000Date of Patent: March 1, 2005Assignee: Rohm and Haas Electric Materials CMP Holdings, Inc.Inventors: Arun Vishwanathan, David B. James, Lee Melbourne Cook, Peter A. Burke, David Shidner
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Publication number: 20050025663Abstract: A reprocessor having a circulation system for circulating a microbial deactivation fluid through a chamber that forms a part of the circulation system. The reprocessor includes a water filtration system for filtering water used in the reprocessor. The water filtration system includes a fluid feed line connectable to a source of pressurized water. A first filter and second filter elements are disposed in the fluid feed line for filtering fluids flowing therethrough. The second filter element is downstream from the first filter element and has the capacity to filter particles smaller than the first filter element. The fluid feed line forms a fluid path for water entering the reprocessor, and defines a portion of a path for microbial deactivation fluid circulated through the circulation system.Type: ApplicationFiled: August 1, 2003Publication date: February 3, 2005Inventors: Peter Burke, Karl Ludwig, Jude Kral, Francis Zelina
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Publication number: 20050020082Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.Type: ApplicationFiled: August 20, 2004Publication date: January 27, 2005Inventors: Arun Vishwanathan, David James, Lee Cook, Peter Burke, David Shidner
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Patent number: 6749485Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness and hydrolytic stability.Type: GrantFiled: September 20, 2000Date of Patent: June 15, 2004Assignee: Rodel Holdings, Inc.Inventors: David B. James, Arun Vishwanathan, Lee Melbourne Cook, Peter A. Burke, David Shidner, Joseph K. So, John V. H. Roberts
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Patent number: 6736709Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing, pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad also exhibits a stable morphology that can be reproduced easily and consistently. The pad surface has macro-texture that includes perforations as well as surface groove designs The surface groove designs have specific relationships between groove depth and overall pad thickness and groove.area and land area.Type: GrantFiled: August 3, 2000Date of Patent: May 18, 2004Assignee: Rodel Holdings, Inc.Inventors: David B. James, Arun Vishwanathan, Lee Melbourne Cook, Peter A. Burke, David Shidner, Joseph K. So, John V. H. Roberts
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Patent number: 6699299Abstract: A composition is provided in the present invention for polishing a composite semiconductor structure containing a metal layer (such as tungsten, aluminum, or copper), a barrier layer (such as tantalum, tantalum nitride, titanium, or titanium nitride), and an insulating layer (such as SiO2). The composition comprises an aqueous medium, an oxidant, an organic polymer that attenuates removal of the oxide film. The composition may optionally comprise a complexing agent and/or a dispersant.Type: GrantFiled: March 20, 2003Date of Patent: March 2, 2004Assignee: Rodel Holdings, Inc.Inventors: Vikas Sachan, Elizabeth A. (Kegerise) Langlois, Qianqiu (Christine) Ye, Keith G. Pierce, Craig D. Lack, Terence M. Thomas, Peter A. Burke, David Gettman, Sarah Lane
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Patent number: 6693035Abstract: A method for chemical mechanical planarization of a semiconductor structure comprised of a conductive metal interconnect layer, a barrier or liner film, and an underlying dielectric layer using a two-step polishing process is provided. In the first step, the conducting metal overburden is substantially removed with little removal of the barrier or liner layer or the underlying dielectric structure. In the second step, the barrier layer is removed with little removal of the underlying dielectric layer. Five different methods and associated slurry compositions are described for the second polishing step, each adjusted to the state of the wafer following the first step of polishing. By using the appropriate method, the integrity of the remaining semiconductor structure can be substantially retained.Type: GrantFiled: October 19, 1999Date of Patent: February 17, 2004Assignee: Rodel Holdings, Inc.Inventors: Vikas Sachan, Peter A. Burke, Elizabeth A. (Kegerise) Langlois, Keith G. Pierce
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Patent number: 6648743Abstract: A polishing pad for use in chemical mechanical polishing of a semiconductor substrate is described. The polishing pad comprises a substantially flat disk having a polishing surface for contacting the substrate. The polishing surface, which has a central region and a peripheral region, is segmented by a set of substantially parallel linear grooves. The grooves include central grooves which traverse the central region of the polishing surface, and peripheral grooves which traverse the peripheral region of the polishing surface. The central grooves have central groove dimensions, including a central groove width and pitch. The peripheral grooves have peripheral groove dimensions, including a peripheral groove width and pitch. At least one of the central groove dimensions, i.e. the width or the pitch, is different from the corresponding peripheral groove dimension.Type: GrantFiled: September 5, 2001Date of Patent: November 18, 2003Assignee: LSI Logic CorporationInventor: Peter A. Burke
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Patent number: 6642597Abstract: Embodiments of the invention include an electrical interconnection structure for connection to large electrical contacts. The electrical interconnection includes a semiconductor substrate having a conductive pad layer formed thereon. A dielectric layer having a plurality of elongate trenches is formed over the conductive pad layer such that the elongate trenches extend through the dielectric layer to the underlying conductive pad layer. Elongate conductive contacts are formed in the elongate trenches to establish electrical connections to the underlying conductive pad layer. The long axes of the elongate bar trenches can be arranged substantially parallel to the long axes of the slots formed in the copper pad. Alternatively, the long axes of the bar trenches can be arranged transversely to the long axes of the slots formed in the copper pad. In some embodiments, the conductive contacts are formed such that they establish electrical connection with sidewalls of the underlying conductive pad layer.Type: GrantFiled: October 16, 2002Date of Patent: November 4, 2003Assignee: LSI Logic CorporationInventors: Peter A. Burke, William K. Barth
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Publication number: 20030181046Abstract: A composition is provided in the present invention for polishing a composite semiconductor structure containing a metal layer (such as tungsten, aluminum, or copper), a barrier layer (such as tantalum, tantalum nitride, titanium, or titanium nitride), and an insulating layer (such as SiO2). The composition comprises an aqueous medium, an oxidant, an organic polymer that attenuates removal of the oxide film. The composition may optionally comprise a complexing agent and/or a dispersant.Type: ApplicationFiled: March 20, 2003Publication date: September 25, 2003Inventors: Vikas Sachan, Elizabeth A. (Kegerise) Langlois, Qianqiu (Christine) Ye, Keith G. Pierce, Craig D. Lack, Terence M. Thomas, Peter A. Burke, David Gettman, Sarah Lane
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Patent number: 6616717Abstract: A composition is provided in the present invention for polishing a composite semiconductor structure containing a metal layer (such as tungsten, aluminum, or copper), a barrier layer (such as tantalum, tantalum nitride, titanium, or titanium nitride), and an insulating layer (such as SiO2). The composition comprises an aqueous medium, an oxidant, an organic polymer that attenuates removal of the oxide film. The composition may optionally comprise a complexing agent and/or a dispersant.Type: GrantFiled: May 16, 2001Date of Patent: September 9, 2003Assignee: Rodel Holdings, Inc.Inventors: Vikas Sachan, Elizabeth A. (Kegerise) Langlois, Qianqiu (Christine) Ye, Keith G. Pierce, Craig D. Lack, Terence M. Thomas, Peter A. Burke, David Gettman, Sarah Lane
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Publication number: 20030164066Abstract: A molten bath-based direct smelting process for producing ferrous metal from a ferrous feed material is disclosed. The process is characterised by injecting pre-heated air downwardly into metallurgical vessel at an angle of 20 to 90° C. relative to a horizontal axis and at a temperature of 800-1400° C. and at a velocity of 200-600 m/s via at least one lance (27). This step forces molten material in the region of a lower end of the lance away from the lance and forming a “free” space around the lower end of the lance that has a concentration of molten material that is lower than the molten material concentration in the raised bath. The process is further characterised in that the lance is located so that: (i) the lance extends into the vessel a distance that is at least the outer diameter of the lower end of the lance; and (ii) the lower end of the lance is at least 3 times the outer diameter of the lower end of the lance above a quiescent surface of the molten bath.Type: ApplicationFiled: January 27, 2003Publication date: September 4, 2003Inventors: Rodney J Dry, Peter Burke
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Patent number: 6602112Abstract: A method for polishing a surface of metal on a semiconductor substrate by using a polishing pad and hydrogen peroxide, and removing particles of metal from the semiconductor substrate by polishing, and dissolving the particles in the quantity of hydrogen peroxide.Type: GrantFiled: January 18, 2001Date of Patent: August 5, 2003Assignee: Rodel Holdings, Inc.Inventors: Tony Quan Tran, Vikas Sachan, David Gettman, Terence M. Thomas, Craig D. Lack, Peter A. Burke
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Publication number: 20030138344Abstract: A system for handling mail is in the form of a modular facility (10), which is capable of being isolated from the surrounding environment. The modular facility includes an enclosure or sorting area (40) for receiving and sorting incoming mail. A decontamination system (22) receives sorted mail and decontaminates the mail with a antimicrobial gas, such as ethylene oxide. A clean room (32), isolated from the enclosure and spaced from the enclosure by the decontamination system, is used for receiving processed mail from the decontamination system and sorting the mail for distribution. A source (92) of a decontaminant gas, such as vapor hydrogen peroxide, is fluidly connected with the enclosure for supplying the decontaminant gas to the enclosure in the event that the sorting room is contaminated or suspected of being contaminated with a pathogenic biological or chemical agent.Type: ApplicationFiled: October 25, 2002Publication date: July 24, 2003Applicant: STERIS INC.Inventors: Thaddeus J. Mielnik, David A. Karle, Alex D. Biggie, William John Thomas Biebesheimer, Peter A. Burke, Gerald E. McDonnell, Chad Rhodes, Elaine M. Kopis
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Patent number: 6582283Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.Type: GrantFiled: July 11, 2002Date of Patent: June 24, 2003Assignee: Rodel Holdings, Inc.Inventors: David B. James, Arun Vishwanathan, Lee Melbourne Cook, Peter A. Burke, David Shidner
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Publication number: 20030027500Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.Type: ApplicationFiled: July 11, 2002Publication date: February 6, 2003Inventors: David B. James, Arun Vishwanathan, Lee Melbourne Cook, Peter A. Burke, David Shidner