Patents by Inventor Peter A. Burke

Peter A. Burke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090315142
    Abstract: A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.
    Type: Application
    Filed: August 27, 2009
    Publication date: December 24, 2009
    Inventors: Peter A. Burke, Sallie Hose, Sudhama C. Shastri
  • Publication number: 20090267187
    Abstract: An energy storage device such as a metal-insulator-metal capacitor and a method for manufacturing the energy storage device. The metal-insulator-metal capacitor includes an insulating material positioned between a bottom electrode or bottom plate and a top electrode or top plate. The surface area of the bottom electrode is greater than the surface area of the insulating material and the surface area of the insulating material is greater than the surface area of the top electrode. The top electrode and the insulating layer have edges that are laterally within and spaced apart from edges of the bottom electrode. A protective layer covers the top electrode, the edges of the top electrode, and the portions of the insulating layer that are uncovered by the top electrode. The protective layer serves as an etch mask during the formation of the bottom electrode.
    Type: Application
    Filed: April 23, 2008
    Publication date: October 29, 2009
    Inventors: Sallie Hose, Derryl Allman, Peter A. Burke, Ponce Saopraseuth
  • Publication number: 20090256217
    Abstract: The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a substantially planar surface of the bottom electrode.
    Type: Application
    Filed: April 14, 2008
    Publication date: October 15, 2009
    Applicant: LSI LOGIC CORPORATION
    Inventors: Hongquiang Lu, Peter A. Burke, Wilbur Catabay
  • Patent number: 7602027
    Abstract: A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: October 13, 2009
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Peter A. Burke, Sallie Hose, Sudhama C. Shastri
  • Publication number: 20090233905
    Abstract: The invention relates to a combination comprising a Bcr-Abl, c-Kit and PDGF-R tyrosine kinase inhibitor; and one or more pharmaceutically active agents; pharmaceutical compositions comprising said combination; methods of treatment comprising said combination; processes for making said combination; and a commercial package comprising said combination.
    Type: Application
    Filed: April 4, 2007
    Publication date: September 17, 2009
    Inventors: Gregory Peter Burke, Ronald Richard Linnartz, Paul W. Manley, Richard William Versace
  • Publication number: 20090195401
    Abstract: Embodiments of the invention may include a sensor system and a method used to track the behaviors of targets in an area under surveillance. The invention may include a sensor array located in the area that is capable of sending messages to a user when behavior of a tracked target is determined to be anomalous. In making the determination of anomalous behavior, the sensor system and method may generate and continuously refine a pattern of life model that may examine, for example, the paths a target may take within the sensor array and the end points of the paths taken. The sensor system and method may also incorporate any user defined conditions for anomalous behavior.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 6, 2009
    Inventors: Andrew Maroney, Peter Burke, Richard French
  • Patent number: 7569182
    Abstract: The present invention provides a method of operating a reprocessor that has a chamber for receiving items to be sterilized. The reprocessor is filled with water that has passed through a first and a second filter element that both comprise a filtration system. A liquid sterilant is generated by mixing the water with dry chemical reagents. The liquid sterilant is circulated through a fluid circulation system and the filtration system wherein a portion of the liquid sterilant is directed through a bypass conduit and another portion is directed through the first and second filter elements. After a predetermined exposure time, the reprocessor is drained. Then the reprocessor is filled with water for rinsing that has passed through the first and the second filter elements. The water for rinsing is heated prior to being introduced into the reprocessor.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: August 4, 2009
    Assignee: American Sterilizer Company
    Inventors: Peter A. Burke, Karl F. Ludwig, Jude A. Kral, Francis J. Zelina
  • Publication number: 20090130739
    Abstract: Compositions and methods for deactivating articles contaminated with nanobacteria, generally comprise a dispersant and/or a dissolution agent, and a deactivator. The methods and compositions of the invention are advantageously utilized to decontaminate and/or sterilize various articles such as medical and manufacturing devices or surfaces.
    Type: Application
    Filed: January 13, 2009
    Publication date: May 21, 2009
    Applicant: AMERICAN STERILIZER COMPANY
    Inventors: Peter A. Burke, Gerald E. McDonnell, Kathleen A. Fix
  • Patent number: 7531442
    Abstract: Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: May 12, 2009
    Assignee: LSI Corporation
    Inventors: Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying, Chiyi Kao, Peter Burke, Ramaswamy Ranganathan, Qwai Low
  • Publication number: 20080310997
    Abstract: A method and apparatus for aerating a region exposed to a gaseous/vaporous sterilant. A catalytic destroyer and a reactive chemical unit are used to reduce the concentration of the gaseous/vaporous sterilant within the region. The reactive chemical unit includes a chemistry that is chemically reactive with the gaseous/vaporous sterilant. In one embodiment, the gaseous/vaporous sterilant is vaporized hydrogen peroxide and the chemistry of the reactive chemical unit includes thiosulfate and iodide.
    Type: Application
    Filed: June 15, 2007
    Publication date: December 18, 2008
    Inventors: Michael A. Centanni, Peter A. Burke
  • Publication number: 20080303155
    Abstract: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.
    Type: Application
    Filed: August 13, 2008
    Publication date: December 11, 2008
    Applicant: LSI CORPORATION
    Inventors: Hong-Qiang LU, Peter A. BURKE, Wilbur G. CATABAY
  • Patent number: 7427563
    Abstract: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: September 23, 2008
    Assignee: LSI Corporation
    Inventors: Hong-Qiang Lu, Peter A. Burke, Wilbur G. Catabay
  • Patent number: 7402770
    Abstract: A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: July 22, 2008
    Assignee: LSI Logic Corporation
    Inventors: Sey-Shing Sun, Hemanshu D. Bhatt, Peter A. Burke, Richard J. Carter
  • Publication number: 20080159270
    Abstract: A node in for connection to a synchronous packet network includes a packet switch and a physical interface for connection to the packet network. A phase locked loop arrangement for synchronization is integrated into the physical interface, the packet switch or both.
    Type: Application
    Filed: December 21, 2007
    Publication date: July 3, 2008
    Applicant: ZARLINK SEMICONDUCTOR INC.
    Inventors: Peter Burke, Louise Gaulin, Silvana Goncala Rodrigues, Daniel Norman Gallant, Maamoun Abou Seido
  • Publication number: 20080157217
    Abstract: A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Peter A. Burke, Sallie Hose, Sudhama C. Shastri
  • Publication number: 20080152544
    Abstract: When microbial contamination is introduced into a room (20*) of an enclosure, such as a building, an HVAC system including supply ductwork (16) and a return ductwork (34) is decontaminated with hydrogen peroxide vapor. A decontamination controller (46) operates controllable baffles (22) at outlet registers (20), temporary controllable baffles (44) at inlet registers (30), and a blower system (10) to circulate hydrogen peroxide vapor from hydrogen peroxide vapor generators (42) through the ductwork in both forward and reverse directions. Further, at least portions of the baffles are closed to create dwell times in which the hydrogen peroxide vapor resides in the ductwork with minimal or turbulent flow.
    Type: Application
    Filed: March 3, 2008
    Publication date: June 26, 2008
    Applicant: STERIS INC.
    Inventors: Iain F. McVey, Victor M. Selig, Lewis I. Schwartz, Gerald E. McDonnell, Peter A. Burke
  • Patent number: 7361304
    Abstract: When microbial contamination is introduced into a room (20*) of an enclosure, such as a building, an HVAC system including supply ductwork (16) and a return ductwork (34) is decontaminated with hydrogen peroxide vapor. A decontamination controller (46) operates controllable baffles (22) at outlet registers (20), temporary controllable baffles (44) at inlet registers (30), and a blower system (10) to circulate hydrogen peroxide vapor from hydrogen peroxide vapor generators (42) through the ductwork in both forward and reverse directions. Further, at least portions of the baffles are closed to create dwell times in which the hydrogen peroxide vapor resides in the ductwork with minimal or turbulent flow.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: April 22, 2008
    Assignee: Steris Inc.
    Inventors: Ian F. McVey, Victor M. Selig, Lewis I. Schwartz, Gerald E. McDonnell, Peter A. Burke
  • Publication number: 20080020130
    Abstract: Systems and methods for synthesizing long carbon nanotubes and using the nanotube as an electrical conductor. A substrate is provided with one or more metal underlayer platforms that allow the nanotube to grow freely suspended from the substrate. A modified gas-flow injector is used to reduce the gas flow turbulence during nanotube growth. Nanotube electrodes are formed by growing arrays of aligned nanotubes between two metal underlayer platforms.
    Type: Application
    Filed: September 12, 2005
    Publication date: January 24, 2008
    Inventors: Peter Burke, Zhen Yu, Shengdong Li
  • Patent number: 7312532
    Abstract: A dual damascene interconnect structure is formed by patterning a first dielectric to form a metal line. A second dielectric is disposed on the first dielectric and patterned to form a via. The first metal line is patterned in a configuration relative to a via landing so that a cavity is formed when the via etch into the second dielectric is extended into the first dielectric. The cavity is filled with a conductive metal in an integral manner with the formation of the via to form a via projection for improved electrical contact between the via and the metal line.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: December 25, 2007
    Assignee: LSI Corporation
    Inventors: Peter A. Burke, William K. Barth, Hongqiang Lu
  • Publication number: 20070272058
    Abstract: The present invention relates to a direct smelting plant and a direct smelting process for producing molten metal from a metalliferous feed material, such as ores, partly reduced ores, and metal-containing waste streams, the latter of which comprising the steps of (a) pretreating metalliferous feed material in a pretreatment unit and producing pretreated feed material having a temperature of at least 200° C., (b) storing pretreated metalliferous feed material having a temperature of at least 200° C. under pressure in a hot feed material storage means, (c) transferring pretreated metalliferous feed material having a temperature of at least 200° C. under pressure in a hot feed material transfer line to a solids delivery means of a direct smelting vessel, and (d) delivering pretreated metalliferous feed material into the direct smelting vessel and smelting metalliferous feed material to molten metal in the vessel.
    Type: Application
    Filed: October 16, 2004
    Publication date: November 29, 2007
    Inventors: Andreas Orth, David Leigh, Peter Burke