Patents by Inventor Peter A. Davison

Peter A. Davison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170032991
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Application
    Filed: October 17, 2016
    Publication date: February 2, 2017
    Inventors: John C. JOHNSON, Sandeep B. SANE, Sandeep RAZDAN, Edward R. PRACK, Leonel R. ARANA, Peter A. DAVISON, Eric J. MORET, Lawrence M. PALANUK, Gregory A. STONE
  • Publication number: 20160172222
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Application
    Filed: February 22, 2016
    Publication date: June 16, 2016
    Inventors: John C. JOHNSON, Sandeep B. SANE, Sandeep RAZDAN, Edward R. PRACK, Leonel R. ARANA, Peter A. DAVISON, Eric J. MORET, Lawrence M. PALANUK, Gregory A. STONE
  • Patent number: 9305816
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 28, 2013
    Date of Patent: April 5, 2016
    Assignee: INTEL CORPORATION
    Inventors: John C. Johnson, Peter A. Davison, Eric J. Moret, Lawrence M. Palanuk, Gregory A. Stone
  • Publication number: 20150187622
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Application
    Filed: December 28, 2013
    Publication date: July 2, 2015
    Inventors: John C. JOHNSON, Sandeep B. SANE, Sandeep RAZDAN, Edward R. PRACK, Leonel R. ARANA, Peter A. DAVISON, Eric J. MORET, Lawrence M. PALANUK, Gregory A. STONE
  • Patent number: 7674729
    Abstract: Embodiments of a method and apparatus for imprinting a trench pattern on a substrate using ultrasonic vibrations. The trench pattern corresponds to a circuit pattern that is to be formed on the substrate, the circuit pattern including a number of conductive traces and other conductive elements. In one embodiment, the substrate includes a base layer and a layer of dielectric material overlying a surface of the base layer, and the circuit pattern is formed in the dielectric layer.
    Type: Grant
    Filed: September 22, 2007
    Date of Patent: March 9, 2010
    Assignee: Intel Corporation
    Inventor: Peter A. Davison
  • Patent number: 7527085
    Abstract: A small water-cooling type electronic component cooling apparatus is provided. The electronic component cooling apparatus comprises a so-called water-cooling heat sink 3, a radiator 7 cooled by an electric fan 5, first and second coolant paths 9, 11 for circulating a coolant between the heat sink 3 and the radiator 7, and an electric pump 13 to supply a moving energy to the coolant. The electric pump 13 is arranged at a position facing the heat-radiating portion of the radiator 7.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: May 5, 2009
    Assignees: Sanyo Denki Co., Ltd., Intel Corporation
    Inventors: Masayuki Iijima, Tomoaki Ikeda, Masashi Miyazawa, Kouji Ueno, Paul J. Gwin, Brian J. Long, Peter A. Davison, Rolf A. Konstad
  • Patent number: 7495623
    Abstract: In some embodiments, an electronic device comprises a circuit board, an antenna structure on the circuit board, and a waveguide mounted on the circuit board above the antenna structure. Other embodiments may be described.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: February 24, 2009
    Inventors: Gary Brist, Bryce Horine, Stephen H. Hall, Peter A. Davison
  • Publication number: 20090001032
    Abstract: Techniques associated with higher performance barrier materials for containers to contain one or more environmentally sensitive devices associated with semiconductor manufacture are generally described. In one example, an apparatus includes an enclosure to contain one or more environmentally sensitive devices associated with semiconductor manufacture, the enclosure comprising a liquid crystal polymer (LCP) to provide a barrier against at least water and oxygen and to reduce purging requirements, and a door coupled with the enclosure.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventor: Peter A. Davison
  • Publication number: 20080224936
    Abstract: In some embodiments, an electronic device comprises a circuit board, an antenna structure on the circuit board, and a waveguide mounted on the circuit board above the antenna structure. Other embodiments may be described.
    Type: Application
    Filed: March 15, 2007
    Publication date: September 18, 2008
    Inventors: Gary Brist, Bryce Horine, Stephen H. Hall, Peter A. Davison
  • Patent number: 7285447
    Abstract: Embodiments of a method and apparatus for imprinting a trench pattern on a substrate using ultrasonic vibrations. The trench pattern corresponds to a circuit pattern that is to be formed on the substrate, the circuit pattern including a number of conductive traces and other conductive elements. In one embodiment, the substrate includes a base layer and a layer of dielectric material overlying a surface of the base layer, and the circuit pattern is formed in the dielectric layer.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: October 23, 2007
    Assignee: Intel Corporation
    Inventor: Peter A. Davison
  • Patent number: 7183140
    Abstract: An injection molded metal bonding tray may be utilized in the fabrication of integrated circuit devices. In one embodiment, a substrate of an integrated circuit device is placed in a pocket of an injection molded metal bonding tray. A plurality of conductors is placed on the substrate and the conductors are bonded to the substrate in an infrared reflow oven, for example. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: Peter A. Davison, Sabina J. Houle
  • Patent number: 6884086
    Abstract: A land grid array (LGA) socket is connected to a power converter using compression contact technology eliminating the need for an edge-card connector typically required in such applications. The LGA socket is mounted to the power converter in a single direction of assembly (i.e., the vertical axis).
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: April 26, 2005
    Assignee: Intel Corporation
    Inventors: Thomas G. Ruttan, Ed Stanford, Peter A. Davison, Tony Harrison
  • Patent number: 6859367
    Abstract: Heat sink attachment components are provided comprising retention bolts with a coil spring captured between the head of the retention bolt and a retention lock flange of a retention lock. A portion of each retention bolt shaft is retained and in frictional engagement with socket bores of a mounting socket. A moderate interference fit between the retention lock and the retention bolt prevents unintended decoupling. While engaged, the compressed coil spring urges against the retention lock flange, with the retention lock flange in urging engagement with the heat dissipation side of a heat sink base, with the heat sink base in urging engagement with thermal interface material on the top of the microelectronic package. The urging engagement of the coil springs provide a constant bias for urging engagement between the components.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: February 22, 2005
    Assignee: Intel Corporation
    Inventor: Peter A. Davison
  • Publication number: 20040266064
    Abstract: Embodiments of a method and apparatus for imprinting a trench pattern on a substrate using ultrasonic vibrations. The trench pattern corresponds to a circuit pattern that is to be formed on the substrate, the circuit pattern including a number of conductive traces and other conductive elements. In one embodiment, the substrate includes a base layer and a layer of dielectric material overlying a surface of the base layer, and the circuit pattern is formed in the dielectric layer.
    Type: Application
    Filed: June 25, 2003
    Publication date: December 30, 2004
    Inventor: Peter A. Davison
  • Patent number: 6809928
    Abstract: According to some embodiments, a cooling system that may be installed in a computer chassis has a fluid-containing space that is sealed and pressurized by an inert gas. The fluid-containing space may be formed from a cold plate that may serve as a heat sink for an integrated circuit, a heat exchanger, tubing, and a pump volume. A coolant may be contained in the fluid-containing space.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: October 26, 2004
    Assignee: Intel Corporation
    Inventors: Paul J. Gwin, Rolf A. Konstad, Peter A. Davison, Mark A. Trautman
  • Publication number: 20040130876
    Abstract: Heat sink attachment components are provided comprising retention bolts with a coil spring captured between the head of the retention bolt and a retention lock flange of a retention lock. A portion of each retention bolt shaft is retained and in frictional engagement with socket bores of a mounting socket. A moderate interference fit between the retention lock and the retention bolt prevents unintended decoupling. While engaged, the compressed coil spring urges against the retention lock flange, with the retention lock flange in urging engagement with the heat dissipation side of a heat sink base, with the heat sink base in urging engagement with thermal interface material on the top of the microelectronic package. The urging engagement of the coil springs provide a constant bias for urging engagement between the components.
    Type: Application
    Filed: January 3, 2003
    Publication date: July 8, 2004
    Inventor: Peter A. Davison
  • Publication number: 20040125561
    Abstract: According to some embodiments, a cooling system that may be installed in a computer chassis has a fluid-containing space that is sealed and pressurized by an inert gas. The fluid-containing space may be formed from a cold plate that may serve as a heat sink for an integrated circuit, a heat exchanger, tubing, and a pump volume. A coolant may be contained in the fluid-containing space.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 1, 2004
    Inventors: Paul J. Gwin, Rolf A. Konstad, Peter A. Davison, Mark A. Trautman
  • Patent number: 6709277
    Abstract: A land grid array (LGA) socket is connected to a power converter using compression contact technology eliminating the need for an edge-card connector typically required in such applications. The LGA socket is mounted to the power converter in a single direction of assembly (i.e., the vertical axis).
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: March 23, 2004
    Assignee: Intel Corporation
    Inventors: Thomas G. Ruttan, Ed Stanford, Peter A. Davison, Tony Harrison
  • Patent number: 6560118
    Abstract: An emblem that is located within a recess of a cover. The cover may be part of a cartridge which also contains a number of integrated circuit packages that are mounted to a printed circuit board. The emblem is typically attached to the cover by an adhesive. The recess reduces the likelihood of the emblem being removed from the cover. The emblem preferably contains a hologram which can identify a type of cartridge produced by a manufacturer.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: May 6, 2003
    Assignee: Intel Corporation
    Inventors: Michael Stark, Michael Rutigliano, Amol Kirtikar, Peter A. Davison
  • Patent number: 6524116
    Abstract: A socket for an electronic assembly. The socket may include a first finger that is coupled to a second finger. The socket may further have a plurality of contacts that are located within contact openings of the first and second fingers. The fingers may be separated by spaces that reduce the effective coefficient of thermal expansion.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: February 25, 2003
    Assignee: Intel Corporation
    Inventors: Peter A. Davison, Michael T. Crocker