Patents by Inventor Peter A. Habitz

Peter A. Habitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080201683
    Abstract: A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
    Type: Application
    Filed: April 24, 2008
    Publication date: August 21, 2008
    Applicant: International Business Machines Corporation
    Inventors: Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Anthony D. Polson
  • Publication number: 20080195993
    Abstract: A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
    Type: Application
    Filed: April 22, 2008
    Publication date: August 14, 2008
    Applicant: International Business Machines Corporation
    Inventors: Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Anthony D. Polson
  • Patent number: 7401307
    Abstract: A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: July 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Jeffrey H. Oppold, Anthony D. Polson
  • Publication number: 20080052656
    Abstract: A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
    Type: Application
    Filed: October 31, 2007
    Publication date: February 28, 2008
    Inventors: Eric Foreman, Peter Habitz, David Hathaway, Jerry Hayes, Jeffrey Oppold, Anthony Polson
  • Publication number: 20080018872
    Abstract: In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
    Type: Application
    Filed: October 1, 2007
    Publication date: January 24, 2008
    Inventors: Robert Allen, John Cohn, Scott Gould, Peter Habitz, Juergen Koehl, Gustavo Tellez, Ivan Wemple, Paul Zuchowski
  • Patent number: 7289659
    Abstract: In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: October 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Allen, John M. Cohn, Scott W. Gould, Peter A. Habitz, Juergen Koehl, Gustavo E. Tellez, Ivan L. Wemple, Paul S. Zuchowski
  • Publication number: 20070226673
    Abstract: Disclosed are embodiments of an interconnection array for a circuit. The interconnection array comprises a victim net that is positioned parallel to and adjacent to sections of multiple crossed aggressor nets, thereby, minimizing the exposure of the circuit to delay or false switching as a result of coupling capacitance. Also, disclosed are embodiments of an associated method of re-routing an interconnection array that incorporates identifying a victim net and at least two aggressor nets and crossing the aggressor nets so that sections of multiple aggressor nets are positioned parallel to and adjacent to the victim net in order to minimizes the impact of coupling capacitance on the victim net with minimal changes to the wiring environment.
    Type: Application
    Filed: March 27, 2006
    Publication date: September 27, 2007
    Inventors: Peter Habitz, William Livingstone
  • Patent number: 7266474
    Abstract: A ring oscillator test structure comprises at least two overlapping rings that are switchable between different numbers of stages. A delay distribution is measured for various numbers of stages in a set of oscillators formed in different locations subject to different systematic delay effects. The delay distributions are analyzed to isolate the systematic and the random contributions to the standard deviation of the distributions.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: September 4, 2007
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Habitz, Jerry D. Hayes
  • Publication number: 20070061771
    Abstract: A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the subset of cell designs determining a respective cell design location of the corresponding shape; determining a common shapes processing rule for all corresponding shapes of each cell design based on the respective cell design locations of each of the corresponding shapes; and performing shapes processing of the corresponding shape only of a single cell design of the subset of cell designs to generate resulting data for the subset of cell designs. Also a computer usable medium including computer readable program code having an algorithm adapted to implement the method for reticle design correction and electrical extraction.
    Type: Application
    Filed: September 15, 2005
    Publication date: March 15, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter Habitz, David Hathaway, Jerry Hayes, Anthony Polson, Tad Wilder
  • Publication number: 20070055487
    Abstract: Forming of a statistical model for a set of independently variable parameters for analysis of a circuit design is disclosed. In one embodiment, a method includes establishing a timing model including delay and delay changes due to process parameter variations (Pi) that impact timing; selecting an element of the circuit design that dominates circuit delay in the timing model; determining a delay sensitivity of each of a set of derived process parameters (Vj) for the element that are linear combinations of the process parameter variations (Pi); and selecting only those derived process parameters with a high sensitivity for use in the statistical model. The invention simplifies the statistical model and reduces the number of calculations require for timing analysis. A method of performing a timing analysis using the simplified statistical model is also disclosed.
    Type: Application
    Filed: September 2, 2005
    Publication date: March 8, 2007
    Inventors: Peter Habitz, Mark Lasher, William Livingstone
  • Publication number: 20070050164
    Abstract: A ring oscillator test structure comprises at least two overlapping rings that are switchable between different numbers of stages. A delay distribution is measured for various numbers of stages in a set of oscillators formed in different locations subject to different systematic delay effects. The delay distributions are analyzed to isolate the systematic and the random contributions to the standard deviation of the distributions.
    Type: Application
    Filed: August 31, 2005
    Publication date: March 1, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter Habitz, Jerry Hayes
  • Patent number: 7181711
    Abstract: A system and method of performing microelectronic chip timing analysis, wherein the method comprises identifying failing timing paths in a chip; prioritizing the failing timing paths in the chip according to a size of random noise events occurring in each timing path; attributing a slack credit statistic for all but highest order random noise events occurring in each timing path; and calculating a worst case timing path scenario based on the prioritized failing timing paths and the slack credit statistic. Preferably, the random noise events comprise non-clock events. Moreover, the random noise events may comprise victim/aggressor net groups belonging to different regularity groups. Preferably, the size of random noise events comprises coupled noise delta delays due to the random noise events occurring in the chip.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: February 20, 2007
    Assignee: International Business Machines Corporation
    Inventors: Eric A. Foreman, Peter A. Habitz, Gregory M. Schaeffer
  • Publication number: 20070001682
    Abstract: Disclosed are a method and a structure for testing location-specific wire delay at a chip-level independent of silicon delay. The invention incorporates the use of a tester embedded in a metal layer of a chip. The tester comprises a ring oscillator that is selectively connected to either a first wire or a second wire by a multiplexer. A monitor measures ring frequencies of the ring oscillator when connected to either the first or second wire. A processor determines the wire delay based upon differences in the ring frequencies. Additional testers or multiple stages of a single tester may be embedded into either the same metal layer at a different location or into a different metal layer to allow for intra-metal layer or inter-metal layer comparisons of wire delay. Since metal capacitance and silicon load remains constant for both the first and second wires and the transient voltage change along the wire is hold small, metal delay is separable from delay due to silicon device performance.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter Habitz, Anthony Polson
  • Publication number: 20060248485
    Abstract: A system and method of performing microelectronic chip timing analysis, wherein the method comprises identifying failing timing paths in a chip; prioritizing the failing timing paths in the chip according to a size of random noise events occurring in each timing path; attributing a slack credit statistic for all but highest order random noise events occurring in each timing path; and calculating a worst case timing path scenario based on the prioritized failing timing paths and the slack credit statistic. Preferably, the random noise events comprise non-clock events. Moreover, the random noise events may comprise victim/aggressor net groups belonging to different regularity groups. Preferably, the size of random noise events comprises coupled noise delta delays due to the random noise events occurring in the chip.
    Type: Application
    Filed: April 27, 2005
    Publication date: November 2, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric Foreman, Peter Habitz, Gregory Schaeffer
  • Publication number: 20060248488
    Abstract: A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
    Type: Application
    Filed: April 27, 2005
    Publication date: November 2, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter Habitz, David Hathaway, Jerry Hayes, Anthony Polson
  • Publication number: 20060195807
    Abstract: Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
    Type: Application
    Filed: May 15, 2006
    Publication date: August 31, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric Foreman, Peter Habitz, David Hathaway, Jerry Hayes, Anthony Polson
  • Patent number: 7089129
    Abstract: A method for performing an electromigration check and detecting EM problems in a device or circuit. The method uses the capacitance and resistance of the conductors of the device or circuit as parameters in determining a power limit that maintains a required temperature environment that ensures the reliability of the device or circuit. The power limit is then used to check each device interconnect to identify the location of potential EM problems. Corrective action is taken to avoid EM problems as they are detected in the device or circuit.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventor: Peter A. Habitz
  • Patent number: 7089143
    Abstract: Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Anthony D. Polson
  • Publication number: 20060101361
    Abstract: A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
    Type: Application
    Filed: November 3, 2004
    Publication date: May 11, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric Foreman, Peter Habitz, David Hathaway, Jerry Hayes, Jeffrey Oppold, Anthony Polson
  • Publication number: 20050273744
    Abstract: The invention provides a method for providing an integrated circuit (6) having a substantially uniform density between parts (10, 12, 14 and 16) of the IC that are non-orthogonally angled. In particular, the invention provides fill tiling patterns (32, 34) oriented substantially parallel to electrical structure regardless of their angle. A method of electrical analysis based on this provision is also provided as is a related program product.
    Type: Application
    Filed: June 20, 2005
    Publication date: December 8, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Allen, John Cohn, Peter Habitz, William Leipold, Ivan Wemple, Paul Zuchowski