Abstract: According to the present embodiment, a method for calculating the parasitic capacitance in a semiconductor device is disclosed. According to the preferred method, a layout file containing the shapes of a semiconductor device is provided. The dimensions of the layout file are then adjusted to wafer dimensions so as reflect actual production devices. The shapes of the layout file are then partitioned into simpler shapes, typically abutted rectangles, called tiles. Each tile is then decomposed into overlap and fringe capacitance components, each component having a uniform capacitance environment with respect to its capacitance elements. The parasitic capacitance of the semiconductor device can thus be accurately computed, with an efficient use of resources. Additionally the preferred embodiment is easily adaptable to a wide range of technology types.

Abstract: A process of forming a lateral PNP transistor includes the steps of: providing a chip of semiconductor material including an isolated N- device region; implanting N dopant material at a relatively low power and low dosage into a selected implant region of the device region; implanting N dopant material at a relatively higher power and higher dosage into the implant region; and forming emitter and collector regions in the device region such that an intrinsic base region is defined between the collector and emitter regions in the implant region.

Abstract: A process of forming a lateral PNP transistor includes the steps of: providing a chip of semiconductor material including an isolated N- device region; implanting N dopant material at a relatively low power and low dosage into a selected implant region of the device region; implanting N dopant material at a relatively higher power and higher dosage into the implant region; and forming emitter and collector regions in the device region such that an intrinsic base region is defined between the collector and emitter regions in the implant region.