Patents by Inventor Peter Almern Losee

Peter Almern Losee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10347489
    Abstract: A method of manufacturing a semiconductor device is presented. The method includes providing a semiconductor layer comprising silicon carbide, wherein the semiconductor layer comprises a first region doped with a first dopant type. The method further includes implanting the semiconductor layer with a second dopant type using a single implantation mask and a substantially similar implantation dose to form a second region and a junction termination extension (JTE) in the semiconductor layer, wherein the implantation dose is in a range from about 2×1013 cm?2 to about 12×1013 cm?2. Semiconductor devices are also presented.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: July 9, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Peter Almern Losee, Alexander Viktorovich Bolotnikov, Stacey Joy Kennerly
  • Publication number: 20190140048
    Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.
    Type: Application
    Filed: June 18, 2018
    Publication date: May 9, 2019
    Inventors: Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee
  • Patent number: 10269951
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor device layer having silicon carbide and having an upper surface and a lower surface. The semiconductor device also includes a heavily doped body region formed in the upper surface of the semiconductor device layer. The semiconductor device further includes a gate stack formed adjacent to and on top of the upper surface of the semiconductor device layer, wherein the gate stack is not formed adjacent to the heavily doped body region.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: April 23, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Peter Almern Losee, Alexander Bolotnikov, Stacey Joy Kennerly, James William Kretchmer
  • Patent number: 10243039
    Abstract: A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: March 26, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Alexander Viktorovich Bolotnikov, Peter Almern Losee, David Alan Lilienfeld, Reza Ghandi
  • Publication number: 20190088479
    Abstract: A method of manufacturing a semiconductor device including performing a first implantation in a semiconductor layer via ion implantation forming a first implantation region and performing a second implantation in the semiconductor layer via ion implantation forming a second implantation region. The first and second implantation overlap with one another and combine to form a connection region extending into the semiconductor layer by a predefined depth.
    Type: Application
    Filed: April 13, 2018
    Publication date: March 21, 2019
    Inventors: Alexander Viktorovich Bolotnikov, Peter Almern Losee, Reza Ghandi, David Alan Lilienfeld
  • Patent number: 10211304
    Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.). A semiconductor device includes a well region extending a first depth into a surface of an epitaxial semiconductor layer positioned above a drift region. The device includes a junction field-effect transistor (JFET) region positioned adjacent to the well region in the epitaxial semiconductor layer. The device also includes a trench extending a second depth into the JFET region, wherein the trench comprises a bottom and a sidewall that extends down to the bottom at an angle relative to the surface of the epitaxial semiconductor layer.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: February 19, 2019
    Assignee: General Electric Company
    Inventors: Peter Almern Losee, Alexander Viktorovich Bolotnikov
  • Patent number: 10199465
    Abstract: A method of fabricating a semiconductor device cell at a surface of a silicon carbide (SiC) semiconductor layer includes forming a segmented source and body contact (SSBC) of the semiconductor device cell over the surface of the SiC semiconductor layer. The SSBC includes a body contact portion disposed over the surface of the semiconductor layer and proximate to a body contact region of the semiconductor device cell, wherein the body contact portion is not disposed over the center of the semiconductor device cell. The SSBC also includes a source contact portion disposed over the surface of the semiconductor layer and proximate to a source contact region of the semiconductor device cell, wherein the at least one source contact portion only partially surrounds the body contact portion of the SSBC.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: February 5, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Alexander Viktorovich Bolotnikov, Peter Almern Losee
  • Patent number: 10192958
    Abstract: A method of fabricating a semiconductor device cell at a surface of a silicon carbide (SiC) semiconductor layer includes forming a segmented source and body contact (SSBC) of the semiconductor device cell over the surface of the SiC semiconductor layer. The SSBC includes a body contact portion disposed over the surface of the semiconductor layer and proximate to a body contact region of the semiconductor device cell, wherein the body contact portion is substantially disposed over the center of the semiconductor device cell. The SSBC also includes at least one source contact portion disposed over the surface of the semiconductor layer and proximate to a source contact region of the semiconductor device cell, wherein the at least one source contact portion only partially surrounds the body contact portion of the SSBC.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: January 29, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Alexander Viktorovich Bolotnikov, Peter Almern Losee
  • Publication number: 20190013311
    Abstract: A gate network of a silicon-carbide (SiC) power conversion device includes a plurality of gate electrodes of SiC metal-oxide-semiconductor-based (MOS-based) transistor device cells disposed in an active area of the SiC power conversion device, and a gate pad disposed in a gate pad and bus area of the SiC power conversion device. The gate network also includes a gate bus disposed in the gate pad and bus area of the SiC power conversion device, wherein the gate bus extends between and electrically connects the gate pad to at least a portion of the plurality of gate electrodes in the active area of the SiC power conversion device. At least a portion of the gate pad, the gate bus, the plurality of gate electrodes, or a combination thereof, of the gate network have a positive temperature coefficient of resistance greater than approximately 2000 parts-per-million per degree Celsius (ppm/° C.).
    Type: Application
    Filed: July 6, 2017
    Publication date: January 10, 2019
    Inventors: Peter Almern Losee, Alexander Viktorovich Bolotnikov, Fabio Carastro, Alvaro Jorge Mari Curbelo
  • Publication number: 20190006529
    Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to SiC super-junction (SJ) power devices. A SiC-SJ device includes a plurality of SiC semiconductor layers of a first conductivity-type, wherein a first and a second SiC semiconductor layer of the plurality of SiC semiconductor layers comprise a termination region disposed adjacent to an active region with an interface formed therebetween, an act wherein the termination region of the first and the second SiC semiconductor layers comprises a plurality of implanted regions of a second conductivity-type, and wherein an effective doping profile of the termination region of the first SiC semiconductor layer is different from an effective doping profile of the termination region of the second SiC semiconductor layer.
    Type: Application
    Filed: December 15, 2015
    Publication date: January 3, 2019
    Inventors: Alexander Viktorovich BOLOTNIKOV, Peter Almern LOSEE, David Alan LILIENFELD, James Jay MCMAHON
  • Publication number: 20180337273
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor device layer having silicon carbide and having an upper surface and a lower surface. The semiconductor device also includes a heavily doped body region formed in the upper surface of the semiconductor device layer. The semiconductor device further includes a gate stack formed adjacent to and on top of the upper surface of the semiconductor device layer, wherein the gate stack is not formed adjacent to the heavily doped body region.
    Type: Application
    Filed: May 16, 2017
    Publication date: November 22, 2018
    Inventors: Peter Almern Losee, Alexander Bolotnikov, Stacey Joy Kennerly, James William Kretchmer
  • Publication number: 20180337171
    Abstract: A semiconductor power conversion device includes a plurality of device cells in different portions of the active area, each including a respective gate electrode. The device includes a gate pad having a plurality of integrated resistors, each having a respective resistance. The device includes a first gate bus extending between the gate pad and the plurality of gate electrodes in a first portion of the active area. The plurality of gate electrodes in the first area is electrically connected to an external gate connection via a first integrated resistor and the first gate bus, and wherein the plurality of gate electrodes in a second portion of the active area is electrically connected to the external gate connection via a second integrated resistor, wherein the first and second integrated resistors have substantially different respective resistance values.
    Type: Application
    Filed: May 18, 2017
    Publication date: November 22, 2018
    Inventors: Peter Almern Losee, Alexander Viktorovich Bolotnikov
  • Patent number: 10096681
    Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to disconnected or connected shielding regions that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a widest portion of the JFET region between adjacent device cells such that a distance between a shielding region and well regions surrounding device cell is less than a parallel JFET width between two adjacent device cells, while maintaining a channel region width and/or a JFET region density that is greater than that of a comparable conventional stripe device. As such, the disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: October 9, 2018
    Assignee: General Electric Company
    Inventors: Alexander Viktorovich Bolotnikov, Peter Almern Losee
  • Patent number: 10056457
    Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of channel region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed channel region extensions have the same conductivity-type as the channel region and extend outwardly from the channel region and into the JFET region of a first device cell such that a distance between the channel region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: August 21, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Alexander Viktorovich Bolotnikov, Peter Almern Losee
  • Patent number: 10002920
    Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 19, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee
  • Publication number: 20180166531
    Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.
    Type: Application
    Filed: December 14, 2016
    Publication date: June 14, 2018
    Inventors: Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee
  • Patent number: 9997507
    Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: June 12, 2018
    Assignee: General Electric Company
    Inventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Rui Zhou, Peter Almern Losee
  • Patent number: 9899512
    Abstract: Embodiments of a silicon carbide (SiC) device are provided herein. In some embodiments, a silicon carbide (SiC) device may include a gate electrode disposed above a SiC semiconductor layer, wherein the SiC semiconductor layer comprises: a drift region having a first conductivity type; a well region disposed adjacent to the drift region, wherein the well region has a second conductivity type; and a source region having the first conductivity type disposed adjacent to the well region, wherein the source region comprises a source contact region and a pinch region, wherein the pinch region is disposed only partially below the gate electrode, wherein a sheet doping density in the pinch region is less than 2.5×1014 cm?2, and wherein the pinch region is configured to deplete at a current density greater than a nominal current density of the SiC device to increase the resistance of the source region.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: February 20, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Peter Almern Losee, Ljubisa Dragoljub Stevanovic, Gregory Thomas Dunne, Alexander Viktorovich Bolotnikov
  • Publication number: 20170345890
    Abstract: Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.
    Type: Application
    Filed: May 26, 2016
    Publication date: November 30, 2017
    Inventors: Peter Almern Losee, Alexander Viktorovich Bolotnikov, Yang Sui
  • Publication number: 20170338314
    Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).
    Type: Application
    Filed: May 15, 2017
    Publication date: November 23, 2017
    Inventors: Alexander Viktorovich Bolotnikov, Peter Almern Losee