Abstract: A semiconductor device is provided. The semiconductor device includes an avalanche photodiode unit and a thyristor unit. The avalanche photodiode unit is configured to receive incident light to generate a trigger current and comprises a wide band-gap semiconductor. The thyristor unit is configured to be activated by the trigger current to an electrically conductive state. A semiconductor device and a method for making a semiconductor device are also presented.

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to active area designs for SiC super-junction (SJ) power devices. A SiC-SJ device includes an active area having one or more charge balance (CB) layers. Each CB layer includes a semiconductor layer having a first conductivity-type and a plurality of floating regions having a second conductivity-type disposed in a surface of the semiconductor layer. The plurality of floating regions and the semiconductor layer are both configured to substantially deplete to provide substantially equal amounts of charge from ionized dopants when a reverse bias is applied to the SiC-SJ device.

Abstract: A semiconductor device may include a substrate comprising silicon carbide; a drift layer disposed over the substrate doped with a first dopant type; an anode region disposed adjacent to the drift layer, wherein the anode region is doped with a second dopant type; and a junction termination extension disposed adjacent to the anode region and extending around the anode region, wherein the junction termination extension has a width and comprises a plurality of discrete regions separated in a first direction and in a second direction and doped with varying concentrations with the second dopant type, so as to have an effective doping profile of the second conductivity type of a functional form that generally decreases along a direction away from an edge of the primary blocking junction.

Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.

Abstract: A semiconductor device may include a drift region having a first conductivity type, a source region having the first conductivity type, and a well region having a second conductivity type disposed adjacent to the drift region and adjacent to the source region. The well region may include a channel region that has the second conductivity type disposed adjacent to the source region and proximal to a surface of the semiconductor device cell. The channel region may include a non-uniform edge that includes at least one protrusion.

Abstract: An insulated gate field-effect transistor (IGFET) device includes a semiconductor body (200) and a gate oxide (234). The semiconductor body includes a first well region (216) doped with a first type of dopant and a second well region (220) that is doped with an opposite, second type of dopant and is located within the first well region. The gate oxide includes a relatively thinner outer section (244) and a relatively thicker interior section (246). The outer section is disposed over the first well region and the second well region. The interior section is disposed over a junction gate field effect transistor region (218) of the semiconductor body doped with the second type of dopant. A conductive channel is formed through the second well region when a gate signal is applied to a gate contact (250) disposed on the gate oxide.

Abstract: A method of fabricating a semiconductor device cell at a surface of a silicon carbide (SiC) semiconductor layer includes forming a segmented source and body contact (SSBC) of the semiconductor device cell over the surface of the SiC semiconductor layer. The SSBC includes a body contact portion disposed over the surface of the semiconductor layer and proximate to a body contact region of the semiconductor device cell, wherein the body contact portion is substantially disposed over the center of the semiconductor device cell. The SSBC also includes at least one source contact portion disposed over the surface of the semiconductor layer and proximate to a source contact region of the semiconductor device cell, wherein the at least one source contact portion only partially surrounds the body contact portion of the SSBC.

Abstract: A method of fabricating a semiconductor device cell at a surface of a silicon carbide (SiC) semiconductor layer includes forming a segmented source and body contact (SSBC) of the semiconductor device cell over the surface of the SiC semiconductor layer. The SSBC includes a body contact portion disposed over the surface of the semiconductor layer and proximate to a body contact region of the semiconductor device cell, wherein the body contact portion is not disposed over the center of the semiconductor device cell. The SSBC also includes a source contact portion disposed over the surface of the semiconductor layer and proximate to a source contact region of the semiconductor device cell, wherein the at least one source contact portion only partially surrounds the body contact portion of the SSBC.

Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.). A semiconductor device includes a well region extending a first depth into a surface of an epitaxial semiconductor layer positioned above a drift region. The device includes a junction field-effect transistor (JFET) region positioned adjacent to the well region in the epitaxial semiconductor layer. The device also includes a trench extending a second depth into the JFET region, wherein the trench comprises a bottom and a sidewall that extends down to the bottom at an angle relative to the surface of the epitaxial semiconductor layer.

Abstract: A semiconductor device includes a silicon carbide (SiC) drift layer disposed on a (0001) oriented SiC substrate. The SiC drift layer has a non-planar surface including a plurality of repeating features that are oriented parallel to a length of a channel of the semiconductor device. Further, the channel region is disposed in a particular crystallographic plane of the SiC drift layer.

Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.

Abstract: An electrical device includes a blocking layer disposed on top of a substrate layer, wherein the blocking layer and the substrate layer each are wide bandgap semiconductors, and the blocking layer and the substrate layer form a buried junction in the electrical device. The device comprises a termination feature disposed at a surface of the blocking layer and a filled trench disposed proximate to the termination feature. The filled trench extends through the blocking layer to reach the substrate layer and is configured to direct an electrical potential associated with the buried junction toward the termination feature disposed near the surface of the blocking layer to terminate the buried junction.

Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Abstract: A semiconductor device includes a drift layer disposed on a substrate. The drift layer has a non-planar surface having a plurality of repeating features oriented parallel to a length of a channel of the semiconductor device. Further, each the repeating features have a dopant concentration higher than a remainder of the drift layer.

Abstract: A semiconductor device includes a silicon carbide (SiC) drift layer disposed on a (0001) oriented SiC substrate. The SiC drift layer has a non-planar surface including a plurality of repeating features that are oriented parallel to a length of a channel of the semiconductor device. Further, the channel region is disposed in a particular crystallographic plane of the SiC drift layer.

Abstract: A method of manufacturing a semiconductor device is presented. The method includes providing a semiconductor layer comprising silicon carbide, wherein the semiconductor layer comprises a first region doped with a first dopant type. The method further includes implanting the semiconductor layer with a second dopant type using a single implantation mask and a substantially similar implantation dose to form a second region and a junction termination extension (JTE) in the semiconductor layer, wherein the implantation dose is in a range from about 2×1013 cm?2 to about 12×1013 cm?2. Semiconductor devices are also presented.

Abstract: A semiconductor device according to one embodiment having a first region comprising a first dopant type, a second region adjacent the first region haivng a second dopant type and a channel region. There is a third region segregated from the channel region having a second dopant type, wherein the third region substantially coincides with the second region.

Abstract: A method comprising, introducing a dopant type into a semiconductor layer to define a well region of the semiconductor layer, the well region comprising a channel region, and introducing a dopant type into the well region to define a multiple implant region substantially coinciding with the well region but excluding the channel region.

Abstract: A thyristor device includes a semiconductor body and a conductive anode. The semiconductor body has a plurality of doped layers forming a plurality of dopant junctions and includes an optical thyristor, a first amplifying thyristor, and a switching thyristor. The conductive anode is disposed on a first side of the semiconductor body. The optical thyristor is configured to receive incident radiation to generate a first electric current, and the first amplifying thyristor is configured to increase the first electric current from the optical thyristor to at least a threshold current. The switching thyristor switches to the conducting state in order to conduct a second electric current from the anode and through the semiconductor body.

Abstract: An electrical device includes a blocking layer disposed on top of a substrate layer, wherein the blocking layer and the substrate layer each are wide bandgap semiconductors, and the blocking layer and the substrate layer form a buried junction in the electrical device. The device comprises a termination feature disposed at a surface of the blocking layer and a filled trench disposed proximate to the termination feature. The filled trench extends through the blocking layer to reach the substrate layer and is configured to direct an electrical potential associated with the buried junction toward the termination feature disposed near the surface of the blocking layer to terminate the buried junction.