Abstract: A processor with multiple execution units for instruction processing is provided. The processor comprises an instruction decode and issue logic and a control logic for resolving register access conflicts between subsequent instructions and a dependency cache, which comprises a receiving logic for receiving an execution unit indicator indicative of the execution unit the instruction is planned to be executed on, a storing logic responsive to the receiving logic for storing the received execution unit indicator, and a retrieving logic responsive to a request from the instruction decode and issue logic for providing the stored execution unit indicator for an instruction. The instruction decode and issue logic is adapted for requesting execution unit indicator for an instruction from the dependency cache and to assign the instruction to one respective of the execution units dependent on the execution unit indicator received from the dependency cache.

Abstract: A method for dynamically selecting a size of a memory access may be provided. The method comprises accessing blocks having a variable number of consecutive cache lines, maintaining a vector with entries of past utilizations for each block size, and adapting said block size before a next access to the blocks.

Abstract: The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.

Abstract: The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.

Abstract: Embodiments of the invention include a computer-implemented method of processor branch prediction. This method aims at training a machine-learning model of processor branch behavior while a processing unit executes computer instructions. Such instructions include branch instructions, load instructions and store instructions. The load instructions and the store instructions cause a control unit of the processing unit to load data from a memory into processor registers and store data from the processor registers to the memory, respectively. Basically, the training of the model involves, for each of N branch instructions (N>2) encountered whilst the processing unit executes said branch instructions: identifying a next branch instruction; and feeding the machine-learning model with carefully chosen inputs.

Abstract: Embodiments of the invention include a computer-implemented method of processor branch prediction. This method aims at training a machine-learning model of processor branch behavior while a processing unit executes computer instructions. Such instructions include branch instructions, load instructions and store instructions. The load instructions and the store instructions cause a control unit of the processing unit to load data from a memory into processor registers and store data from the processor registers to the memory, respectively. Basically, the training of the model involves, for each of N branch instructions (N>2) encountered whilst the processing unit executes said branch instructions: identifying a next branch instruction; and feeding the machine-learning model with carefully chosen inputs.

Abstract: The present disclosure relates to a binding molecule binding to L1, which is capable of binding to the same L1 epitope recognized by the monoclonal antibody L1-OV52.24, and/or which competes with the monoclonal antibody L1-OV52.24 for binding to L1, wherein the variable part of the light chain of L1-OV52.24 comprises the sequence according to SEQ ID No: 1 or wherein the light chain is encoded by SEQ ID No: 3, and wherein the variable part of the heavy chain of L1-OV52.24 comprises the sequence according to SEQ ID No: 2 or wherein the heavy chain is encoded by SEQ ID No: 4, nucleic acids encoding the binding molecules, uses thereof and pharmaceutical compositions comprising the binding molecules.

Abstract: A processor with multiple execution units for instruction processing is provided. The processor comprises an instruction decode and issue logic and a control logic for resolving register access conflicts between subsequent instructions and a dependency cache, which comprises a receiving logic for receiving an execution unit indicator indicative of the execution unit the instruction is planned to be executed on, a storing logic responsive to the receiving logic for storing the received execution unit indicator, and a retrieving logic responsive to a request from the instruction decode and issue logic for providing the stored execution unit indicator for an instruction. The instruction decode and issue logic is adapted for requesting execution unit indicator for an instruction from the dependency cache and to assign the instruction to one respective of the execution units dependent on the execution unit indicator received from the dependency cache.

Abstract: A processor with multiple execution units for instruction processing is provided. The processor comprises an instruction decode and issue logic and a control logic for resolving register access conflicts between subsequent instructions and a dependency cache, which comprises a receiving logic for receiving an execution unit indicator indicative of the execution unit the instruction is planned to be executed on, a storing logic responsive to the receiving logic for storing the received execution unit indicator, and a retrieving logic responsive to a request from the instruction decode and issue logic for providing the stored execution unit indicator for an instruction. The instruction decode and issue logic is adapted for requesting execution unit indicator for an instruction from the dependency cache and to assign the instruction to one respective of the execution units dependent on the execution unit indicator received from the dependency cache.

Abstract: The present invention relates to the anti-L1 monoclonal antibody 9.3 as well as to related antibodies or binding molecules and well as to the uses thereof, especially in tumor treatment.

Abstract: The present invention relates to the anti-L1 monoclonal antibody 9.3 as well as to related antibodies or binding molecules and well as to the uses thereof, especially in tumor treatment.

Abstract: The present invention relates to the anti-L1 monoclonal antibody 9.3 as well as to related antibodies or binding molecules and well as to the uses thereof, especially in tumor treatment.

Abstract: The invention discloses a method of prenatal diagnosis comprising the step of isolating exosomes from an isolated fluid, wherein the exosomes are identified by biomarker detection. Furthermore, the invention discloses the isolation of exosomes from an isolated fluid and the use of a biomarker, particularly CD24 to isolate exosomes from an isolated fluid.

Abstract: The present invention relates to the anti-L1 monoclonal antibody 9.3 as well as to related antibodies or binding molecules and well as to the uses thereof, especially in tumor treatment.

Abstract: The present invention is a system for enhancing the decoding performance of text indexes of an indexed collection of text documents. The posting list includes a plurality of list entries being of variable size depending on the value stored in each posting list entry. The inventive system is based on a statistical analysis of the posting list entries of the plurality of list entries. Prior to decoding, the system can select a decoding routine being appropriate to decode the most frequent type of posting list entries or of a plurality of various posting list entries. After selecting a particular decoding routine and executing the decoding routine for decoding of the entire posting list, a failure check is performed. In the exceptional case that a failure has occurred, a second alternative decoding routine is selected and executed.

Abstract: The present invention relates to the anti-L1 monoclonal antibody 9.3 as well as to related antibodies or binding molecules and well as to the uses thereof, especially in tumor treatment.

Abstract: Described is a pharmaceutical composition comprising a compound(s) interfering with the biological activity of L1 and/or ADAM10 or their expression. Also described is the use of said compound(s) for the prevention/treatment of carcinomas like ovarian and endometrial carcinoma. Finally, the diagnosis of highly malignant forms of carcinomas which is based on the determination of the activity/expression of L1 and/or ADAM10 is described.

Abstract: The present invention relates to an anti L1-CAM antibody for use in a method for the treatment of a disease in a patient which can be treated by inhibition of angiogenesis, wherein the administration of said anti L1-CAM antibody results in the inhibition of angiogenesis and/or tumor metastasis.

Abstract: The present invention relates to a method of generating a distributed text index for parallel query processing by a number of nodes. A set of node indices is generated for text indexing a set of documents, each node text index covering a subset of the documents. For each node text index, a local frequency measure for each term of the node text index is calculated on the basis of a frequency of documents containing the term in the subset of the documents of the node. A global frequency measure for each term is calculated on the basis of a frequency of documents containing the term in the set of documents. A quality measure for each node text index is calculated on the basis of the local frequency measures of the terms of the node and the global frequency measure of the terms of the node.

Abstract: A method for autonomous dynamic voltage (v) and frequency (f) scaling (DVFS) of a microprocessor, wherein autonomous detection of phases of high microprocessor workload and prediction of their duration is performed (PID). The microprocessor frequency (f) will be temporarily increased (LUT) to an appropriate safe value (even beyond its nominal frequency) consistent with technological and ambient constraints in order to improve performance when the computer system comprising the microprocessor benefits most, while during phases of low microprocessor workload its frequency (f) and voltage (v) will be decreased to save energy. This technique exploits hidden performance capabilities and improves the total performance of a computer system without compromising operational stability. No additional hardware such as service processors is needed for contemporary computer systems supporting performance counters and DFVS already.