Abstract: Methods and systems for determining the error vector magnitudes for an RF device by fitting voltage magnitudes to a Rayleigh distribution to produce weighting parameters for an EVM calculation, either in simulation for designing the RF device or as validation measurements from a physical RF device.

Abstract: A phase shifter cell and multiple coupled phase shifter cells that mitigate signal glitches arising from phase state changes by a combination of design architecture and control signal timing. Specifically, one or more of the following three concepts are employed to mitigate insertion loss glitches and control phase behavior during phase state transitions: the timing of switching for each switched half-cell (e.g., including series and/or shunt reactance elements, such as inductors and/or capacitors) within a phase shifter cell is controlled in such a way that the reactance elements do not all switch at the same time; use of a “make before break” timing scheme for combination or “multi-state” phase shifter cells; and/or arranging the timing of each phase shifter cell in a set of multiple coupled phase shifter cells such that the individual cells do not all switch at the same time.

Abstract: A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.

Abstract: Methods and devices to reduce the gate-induced drain/body leakage current (GIDL) generated in FET switch stacks when in OFF state are disclosed. Such devices include inductors as part of bias networks coupled with drain/source terminals and/or body terminals of the transistors within the switch stack. Hybrid approaches where resistors in combination with inductors are implemented as part the bias network are also described.

Abstract: Circuits and methods that enable stable and reliable “hot switching” from one antenna to another without turning RF power to the antennas OFF in wireless RF systems during at least some transmission events. One embodiment comprises an RF switch circuit including a common port configured to pass an RF signal, a plurality of switch arms each coupled to the common port and including an associated port, and a shunt termination impedance selectively couplable to the common port through a switch. Another embodiment comprises a method for switching an RF signal applied to a common port of a switch from a first switch arm initially in an ON state to a second switch arm initially in an OFF state, including: setting the second switch arm to the ON state, and then setting the first switch arm to the OFF state.

Abstract: Methods and systems for determining the error vector magnitudes for an RF device by fitting voltage magnitudes to a Rayleigh distribution to produce weighting parameters for an EVM calculation, either in simulation for designing the RF device or as validation measurements from a physical RF device.

Abstract: A phase shifter cell and multiple coupled phase shifter cells that mitigate signal glitches arising from phase state changes by a combination of design architecture and control signal timing. Specifically, one or more of the following three concepts are employed to mitigate insertion loss glitches and control phase behavior during phase state transitions: the timing of switching for each switched half-cell (e.g., including series and/or shunt reactance elements, such as inductors and/or capacitors) within a phase shifter cell is controlled in such a way that the reactance elements do not all switch at the same time; use of a “make before break” timing scheme for combination or “multi-state” phase shifter cells; and/or arranging the timing of each phase shifter cell in a set of multiple coupled phase shifter cells such that the individual cells do not all switch at the same time.

Abstract: Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

Abstract: Systems and methods for better utilizing available resources within a wireless telecommunication system. One aspect of the present invention is user equipment (UE) configured to autonomously determine its Maximum Sensitivity Degradation (MSD) value for a particular UE configuration. The MSD value is a function of (1) selected UE-specific parameters, such as those that are determined by the characteristics of the UE's RFFE components and RFFE architecture, and (2) selected standard parameters that may be dynamic or vary over time. Another aspect of the present invention is to configure a UE to provide its determined MSD value to a communications network, either as a raw value or as a computed indication of the MSD value relative to a specified reference value. The determined MSD value may then be used by a system controller to select a more efficient allocation of spectrum and network resources.

Abstract: Circuits and methods that provide fine-resolution measurements of RF signal power within a communication system band, thereby more accurately measuring RF interference or the potential of RF interference. One aspect of embodiments of the present invention is a narrow-band tunable filter that includes two elements coupled in series, a periodic passband filter and a tunable filter. The purpose of the periodic passband filter is to generate multiple periodic passbands for an applied RF signal. The purpose of the tunable filter is to generate a single passband, generally with a tunable center frequency. By serially coupling the two filter types in either order, the single passband of the tunable filter is superimposed over one of the periodic passbands of the periodic passband filter, synergistically resulting in an extremely narrow passband.

Abstract: A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.

Abstract: Quarter-wavelength switchable directional coupler architectures and methods that that use intermediate terminated states during directional mode-switching events to prevent generation of reflection coefficients that cause spur generation. A first embodiment of the invention utilizes existing circuitry within a quarter-wavelength switchable directional coupler but alters the conventional mode-switching sequence by adding new stage sequences to effectuate intermediate terminated states to mitigate or prevent spurs. A second embodiment of the invention modifies existing circuitry within a quarter-wavelength switchable directional coupler by adding a cross-coupled intermediate-stage termination circuit, and alters the conventional mode-switching sequence by adding new stage sequences to effectuate intermediate terminated states to mitigate or prevent spurs.

Abstract: Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

Abstract: Antenna structures that can be located in close proximity with respect to an associated RFFE IC regardless of antenna element size. An antenna structure, including a grid or planar antenna or an array of antenna elements, is co-fabricated as part of or with one or more associated RFFE ICs using 3-D stacking of IC dies, either directly or as part of an embedded die packaging technology. Some embodiments include a combinable co-fabricated antenna element, including at least one internally co-fabricated RF antenna element configured to be electrically connectable to a corresponding RF antenna element in a second combinable co-fabricated antenna element by means of 3-D integrated circuit stacking. Some embodiments include a plurality of combinable co-fabricated antenna elements coupled together by means of 3-D integrated circuit stacking such that the antenna elements form a grid antenna or comprise an array of antenna patches.

Abstract: Methods and devices to reduce the gate-induced drain/body leakage current (GIDL) generated in FET switch stacks when in OFF state are disclosed. Such devices include inductors as part of bias networks coupled with drain/source terminals and/or body terminals of the transistors within the switch stack. Hybrid approaches where resistors in combination with inductors are implemented as part the bias network are also described.

Abstract: A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.

Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.

Abstract: Methods and devices to reduce the gate-induced drain/body leakage current (GIDL) generated in FET switch stacks when in OFF state are disclosed. Such devices include inductors as part of bias networks coupled with drain/source terminals and/or body terminals of the transistors within the switch stack. Hybrid approaches where resistors in combination with inductors are implemented as part the bias network are also described.

Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.

Abstract: Methods and systems for frequency band allocation are provided. A tunable/selectable passband filter is disclosed that changes based on the time and location of the user equipment. Additionally, a method of allocating and optimizing upload and download bands is provided to mitigate inter-modulation distortion due to intermodular distortion effects from strong uplink channels.