Patents by Inventor Peter Baumgartner
Peter Baumgartner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250006668Abstract: Waveguide structures are built into integrated circuit devices using standard processing steps for semiconductor device fabrication. A waveguide may include a base, a top, and two side walls. At least one of the walls (e.g., the base or the top) may be formed in a metal layer. The base or top may be patterned to provide a transition to a planar transmission line, such as a coplanar waveguide. The side walls may be formed using vias.Type: ApplicationFiled: June 27, 2023Publication date: January 2, 2025Inventors: Carla Moran Guizan, Peter Baumgartner, Michael Langenbuch, Mamatha Yakkegondi Virupakshappa, Jonathan Jensen, Roshini Sachithanandan, Philipp Riess
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Publication number: 20250006630Abstract: Described herein are integrated circuit devices that include conductive structures formed by direct bonding of different components, e.g., direct bonding of two dies, or of a die to a wafer. The conductive structures are formed from a top metallization layer of each of the components. For example, elongated conductive structures at the top metallization layer may be patterned and bonded to form large interconnects for high-frequency and/or high-power signals. In another example, the bonded conductive structures may form radio frequency passive devices, such as inductors or transformers.Type: ApplicationFiled: June 27, 2023Publication date: January 2, 2025Applicant: Intel CorporationInventors: Carla Moran Guizan, Peter Baumgartner, Thomas Wagner, Georg Seidemann, Michael Langenbuch, Mamatha Yakkegondi Virupakshappa, Jonathan Jensen, Roshini Sachithanandan, Philipp Riess
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Publication number: 20240429888Abstract: An integrated circuit device includes a variable gain amplifier with multiple gain circuits coupled in parallel, where one or more of the multiple gain circuits comprises a first differential pair of transistors, and a complementarily switched second differential pair of transistors cross-connected to the first differential pair of transistors with a sign inversion relative to the first differential pair of transistors. Other examples are disclosed and claimed.Type: ApplicationFiled: June 21, 2023Publication date: December 26, 2024Applicant: Intel CorporationInventors: Ritesh Bhat, Steven Callender, Peter Baumgartner
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Publication number: 20240387353Abstract: Methods and apparatus are disclosed for implementing capacitors in semiconductor devices. An example semiconductor die includes a first dielectric material disposed between a first metal interconnect and a second metal interconnect; and a capacitor positioned within a via extending through the first dielectric material between the first and second metal interconnects, the capacitor including a second dielectric material disposed in the via between the first and second metal interconnects.Type: ApplicationFiled: May 19, 2023Publication date: November 21, 2024Inventors: Michael Langenbuch, Carla Moran Guizan, Mamatha Yakkegondi Virupakshappa, Roshini Sachithanandan, Philipp Riess, Jonathan Jensen, Peter Baumgartner, Georg Seidemann
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Publication number: 20240322775Abstract: Disclosed herein are electronic assemblies, integrated circuit (IC) packages, and communication devices implementing three-dimensional power combiners. An electronic assembly may include a first die, comprising a first transmission line, and a second die, comprising a second transmission line. Each die includes a first face and an opposing second face, and the second die is stacked above the first die so that the first face of the second die is coupled to the second face of the first die. The electronic assembly further includes a first conductive pathway between one end of the first transmission line and a first connection point at the first face of the first die, a second conductive pathway between one end of the second transmission line and a second connection point at the first face of the first die, and a third conductive pathway between the other ends of the first and second transmission lines.Type: ApplicationFiled: March 21, 2023Publication date: September 26, 2024Applicant: Intel CorporationInventors: Telesphor Kamgaing, Peter Baumgartner, Steven Callender, Richard Geiger, Harald Gossner, Jonathan Jensen
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Patent number: 12034085Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.Type: GrantFiled: June 23, 2022Date of Patent: July 9, 2024Assignee: Intel CorporationInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Publication number: 20230252214Abstract: Methods for providing fill patterns for IC devices are disclosed. An example method includes detecting a first device and a second device in an image, e.g., a two- or three-dimensional image representing the IC device. A line is defined based on the devices. The line divides the image into a first section and a second section. A first structure is generated based on the first device. A second structure is generated based on the second device. The second structure is a mirror image of the first structure across the line. A first fill pattern is generated in the first section based on the first structure. A second fill pattern is generated in the second section based on the first fill pattern, e.g., through a reflection transformation of the first fill pattern across the line. The two fill patterns represent patterns of fill structures to be included in the IC device.Type: ApplicationFiled: February 8, 2022Publication date: August 10, 2023Inventors: Richard Hudeczek, Carla Moran Guizan, Peter Baumgartner, Richard Geiger, Alexander Bechtold, Uwe Hodel, Walther Lutz, Georgios Panagopoulos, Johannes Xaver Rauh, Roshini Sachithanandan
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Publication number: 20230197527Abstract: IC devices including semiconductor devices isolated by BSRs are disclosed. An example IC device includes a first and a second semiconductor devices, a support structure, and a BSR. The BSR defines boundaries of a first and second section in the support structure. At least a portion of the first semiconductor device is in the first section, and at least a portion of the second semiconductor device is in the second section. The first semiconductor device is isolated from the second semiconductor device by the BSR. Signals from the first semiconductor device would not be transmitted to the second semiconductor device through the support structure. The BSR may be connected to a TSV or be biased. The IC device may include additional BSRs to isolate the first and second semiconductor devices. An BSR may be a power rail used for delivering power.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Richard Geiger, Peter Baumgartner, Alexander Bechtold, Uwe Hodel, Richard Hudeczek, Walther Lutz, Carla Moran Guizan, Georgios Panagopoulos, Johannes Xaver Rauh, Roshini Sachithanandan
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Publication number: 20230197615Abstract: IC devices including transformers that includes two electrically conductive layers are disclosed. An example IC device includes a transformer that includes a first coil, a second coil, and a magnetic core coupled to the two coils. The first coil includes a portion or the whole electrically conductive layers at the backside of a support structure. The second coil includes a portion or the whole electrically conductive layers at either the frontside or the backside of the support structure. The two coils may have a lateral coupling, vertical coupling, or other types of couplings. The transformer is coupled to a semiconductor device over or at least partially in the support structure. The semiconductor device may be at the frontside of the support structure. The transformer can be coupled to the semiconductor device by TSVs. The IC device may also include BPRs that facilitate backside power delivery to the semiconductor device.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Peter Baumgartner, Bernd Waidhas, Wolfgang Molzer, Klaus Herold, Joachim Singer, Michael Langenbuch, Thomas Wagner
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Publication number: 20230197598Abstract: IC devices including inductors or transformers formed based on BPRs are disclosed. An example IC device includes semiconductor structures of one or more transistors, an electrically conductive layer, a support structure comprising a semiconductor material, and an inductor. The inductor includes an electrical conductor constituted by a power rail buried in the support structure. The inductor also includes a magnetic core coupled to the electrical conductor. The magnetic core includes magnetic rails buried in the support structure, magnetic TSVs buried in the support structure, and a magnetic plate at the backside of the support structure. The magnetic core includes a magnetic material, such as Fe, NiFe, CoZrTa, etc. In some embodiments, the IC device includes another power rail that is buried in the support structure and constitutes another electrical conductor coupled to the magnetic core. The two power rails and magnetic core can constitute a transformer.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Georgios Panagopoulos, Richard Geiger, Peter Baumgartner, Harald Gossner, Uwe Hodel, Michael Langenbuch, Johannes Xaver Rauh, Alexander Bechtold, Richard Hudeczek, Carla Moran Guizan
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Publication number: 20230187313Abstract: IC devices including transmission lines are disclosed. An example IC device includes two electrically conductive layers (first and second layers) and a support structure between the two electrically conductive layers. The first layer is coupled to transistors over or at least partially in the support structure. A shield of a transmission is placed in the first layer. Conductors of the transmission line are placed in the second layer and are coupled to the first layer by TSVs. Another example IC device includes three electrically conductive layers (first, second, and third layers). The first layer is coupled to transistors over or at least partially in the support structure. A shield of a transmission line is placed in the second layer and conductors of the transmission line are placed in the third layer. The conductors are coupled to the first layer by TSVs and coupled to the second layer by vias.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Applicant: Intel CorporationInventors: Carla Moran Guizan, Peter Baumgartner, Richard Geiger, Alexander Bechtold, Uwe Hodel, Richard Hudeczek, Walther Lutz, Georgios Panagopoulos, Johannes Xaver Rauh, Roshini Sachithanandan
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Publication number: 20230068318Abstract: Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×1017 dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 1017 dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Applicant: Intel CorporationInventors: Richard Geiger, Georgios Panagopoulos, Luis Felipe Giles, Peter Baumgartner, Harald Gossner, Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then
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Patent number: 11545586Abstract: A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 29, 2017Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Publication number: 20220320350Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.Type: ApplicationFiled: June 23, 2022Publication date: October 6, 2022Applicant: Intel CorporationInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Patent number: 11424354Abstract: A Group III-Nitride (III-N) device structure is provided comprising: a heterostructure having three or more layers comprising III-N material, an anode n+ region and a cathode comprising donor dopants, wherein the anode n+ region and the cathode are on the first layer of the heterostructure and wherein the anode n+ region and the cathode extend beyond the heterostructure, and an anode metal region within a recess that extends through two or more of the layers, wherein the anode metal region is in electrical contact with the first layer, wherein the anode metal region comprises a first width within the recess and a second width beyond the recess, and wherein the anode metal region is coupled with the anode n+ region. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 29, 2017Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger
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Patent number: 11380806Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.Type: GrantFiled: September 28, 2017Date of Patent: July 5, 2022Assignee: Intel CorporationInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Patent number: 11373995Abstract: A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising III-N material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure, an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 29, 2017Date of Patent: June 28, 2022Assignee: Intel CorporationInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Patent number: 11201151Abstract: Embodiments disclosed herein include resonators, such as resonant fin transistors (RFTs). In an embodiment a resonator comprises a substrate, a set of contact fins over the substrate, a first contact proximate to a first end of the set of contact fins, and a second contact proximate to a second end of the set of contact fins. In an embodiment, the resonator further comprises a set of skip fins over the substrate and adjacent to the set of contact fins. In an embodiment, the resonator further comprises a gate electrode over the set of contact fins and the set of skip fins, wherein the gate electrode is between the first contact and the second contact.Type: GrantFiled: March 27, 2020Date of Patent: December 14, 2021Assignee: Intel CorporationInventors: Richard Hudeczek, Philipp Riess, Richard Geiger, Peter Baumgartner
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Publication number: 20210281286Abstract: Radio frequency shielding within a semiconductor package is described. In one example, a multiple chip package has a digital chip, a radio frequency chip, and an isolation layer between the digital chip and the radio frequency chip. A cover encloses the digital chip and the radio frequency chip.Type: ApplicationFiled: May 24, 2021Publication date: September 9, 2021Inventors: Edmund Goetz, Bernd Mwmmler, Jan-Erik Mueller, Peter Baumgartner
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Patent number: 11024712Abstract: A semiconductor device is proposed. The semiconductor device includes a source region of a field effect transistor having a first conductivity type, a body region of the field effect transistor having a second conductivity type, and a drain region of the field effect transistor having the first conductivity type. The source region, the drain region, and the body region are located in a semiconductor substrate of the semiconductor device and the body region is located between the source region and the drain region. The drain region extends from the body region through a buried portion of the drain region to a drain contact portion of the drain region located at a surface of the semiconductor substrate, the buried portion of the drain region is located beneath a spacer doping region, and the spacer doping region is located within the semiconductor substrate.Type: GrantFiled: June 27, 2018Date of Patent: June 1, 2021Assignee: Intel IP CorporationInventors: Vase Jovanov, Peter Baumgartner, Gregor Bracher, Luis Giles, Uwe Hodel, Andreas Lachmann, Philipp Riess, Karl-Henrik Ryden