Abstract: Embodiments herein relate to compute-in-memory. In one aspect, memory cells in an array include a larger, primary element and a smaller, secondary element in parallel. The memory cells are phase-change memory (PCM) cells in an example implementation. The second elements are pre-programmed to narrow a conductivity distribution of a column of cells. The pre-programming is based on a measured conductivity distribution of the primary elements of the column. In another aspect, selected memory cells in an array are read using an alternating current (AC) signal which reduces sensing noise. Different bit lines can receive signals with different frequencies and/or amplitudes.

Abstract: IC devices including semiconductor devices isolated by BSRs are disclosed. An example IC device includes a first and a second semiconductor devices, a support structure, and a BSR. The BSR defines boundaries of a first and second section in the support structure. At least a portion of the first semiconductor device is in the first section, and at least a portion of the second semiconductor device is in the second section. The first semiconductor device is isolated from the second semiconductor device by the BSR. Signals from the first semiconductor device would not be transmitted to the second semiconductor device through the support structure. The BSR may be connected to a TSV or be biased. The IC device may include additional BSRs to isolate the first and second semiconductor devices. An BSR may be a power rail used for delivering power.

Abstract: IC devices including transmission lines are disclosed. An example IC device includes two electrically conductive layers (first and second layers) and a support structure between the two electrically conductive layers. The first layer is coupled to transistors over or at least partially in the support structure. A shield of a transmission is placed in the first layer. Conductors of the transmission line are placed in the second layer and are coupled to the first layer by TSVs. Another example IC device includes three electrically conductive layers (first, second, and third layers). The first layer is coupled to transistors over or at least partially in the support structure. A shield of a transmission line is placed in the second layer and conductors of the transmission line are placed in the third layer. The conductors are coupled to the first layer by TSVs and coupled to the second layer by vias.

Abstract: A computerized method of controlling a brake assembly applied to a wheel includes receiving, by a decoder circuit, an input signal from a sensor. The input signal indicates rotational speed of a wheel of a vehicle. The method also includes determining, by the decoder circuit, which sensor protocol from a set of sensor protocols is currently being used. The method further includes transforming, by the decoder circuit, the input signal to generate an output signal. The decoder circuit sets a pulse width of the output signal based on the determined sensor protocol. The method also includes transmitting, by the decoder circuit, the output signal to a controller. The method additionally includes determining, by the controller, an operational status of the wheel based on the output signal. The method also includes controlling, by the controller, application of the brake assembly to the wheel based on the operational status.

Abstract: Radio frequency shielding within a semiconductor package is described. In one example, a multiple chip package has a digital chip, a radio frequency chip, and an isolation layer between the digital chip and the radio frequency chip. A cover encloses the digital chip and the radio frequency chip.

Abstract: Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×1017 dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 1017 dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.

Abstract: Radio frequency shielding within a semiconductor package is described. In one example, a multiple chip package has a digital chip, a radio frequency chip, and an isolation layer between the digital chip and the radio frequency chip. A cover encloses the digital chip and the radio frequency chip.

Abstract: A semiconductor die is disclosed, including a plurality of transistors at a frontside of a semiconductor substrate, a backside inductor at a backside of the semiconductor substrate; and a frontside inductor at the frontside of the semiconductor substrate. The frontside inductor and the backside inductor are inductively coupled.

Abstract: Waveguide structures are built into integrated circuit devices using standard processing steps for semiconductor device fabrication. A waveguide may include a base, a top, and two side walls. At least one of the walls (e.g., the base or the top) may be formed in a metal layer. The base or top may be patterned to provide a transition to a planar transmission line, such as a coplanar waveguide. The side walls may be formed using vias.

Abstract: Described herein are integrated circuit devices that include conductive structures formed by direct bonding of different components, e.g., direct bonding of two dies, or of a die to a wafer. The conductive structures are formed from a top metallization layer of each of the components. For example, elongated conductive structures at the top metallization layer may be patterned and bonded to form large interconnects for high-frequency and/or high-power signals. In another example, the bonded conductive structures may form radio frequency passive devices, such as inductors or transformers.

Abstract: Structures having vertical-transport field effect transistors (FETs) with bottom source connection are described. In an example, an integrated circuit structure includes a channel structure above a substrate. A gate structure is laterally surrounding the channel structure. A drain structure is above the gate structure and on the channel structure. A metal source structure is below the substrate and vertically beneath the channel structure. A conductive via is through the substrate, the conductive via coupling the metal source structure to the channel structure.

Abstract: Embodiments disclosed herein include communication dies for mm-wave and/or sub-terahertz wavelength communications. In an embodiment, a communications die comprises a substrate with a first face and a second face. In an embodiment, edge surfaces connect the first face to the second face. In an embodiment, a circuitry element is on the first face, and an antenna on at least one of the edge surfaces.

Abstract: An integrated circuit device includes a variable gain amplifier with multiple gain circuits coupled in parallel, where one or more of the multiple gain circuits comprises a first differential pair of transistors, and a complementarily switched second differential pair of transistors cross-connected to the first differential pair of transistors with a sign inversion relative to the first differential pair of transistors. Other examples are disclosed and claimed.

Abstract: Integrated capacitors are described. In an example, an integrated capacitor structure includes alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together. A metal plate is over or beneath the alternating first metal lines and second metal lines. A dielectric liner layer is between the alternating first metal lines and second metal lines and the metal plate.

Abstract: Integrated capacitors are described. In an example, an integrated capacitor structure includes alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together. A metal plate is over or beneath the alternating first metal lines and second metal lines. The metal plate is coupled to the first metal lines or the second metal lines by vias.

Abstract: A non-transitory computer readable medium having instructions stored therein that when executed by a processor cause the processor to: determine a time difference between a first reference point of a first signal and a second reference point of a second signal, the first signal modulated with a first frequency, and the second signal modulated with a second frequency different from the first frequency; to determine a phase noise based on the determined time difference; and to use the determined phase noise for processing a signal associated with the first signal.

Abstract: Methods and apparatus are disclosed for implementing capacitors in semiconductor devices. An example semiconductor die includes a first dielectric material disposed between a first metal interconnect and a second metal interconnect; and a capacitor positioned within a via extending through the first dielectric material between the first and second metal interconnects, the capacitor including a second dielectric material disposed in the via between the first and second metal interconnects.

Abstract: Disclosed herein are electronic assemblies, integrated circuit (IC) packages, and communication devices implementing three-dimensional power combiners. An electronic assembly may include a first die, comprising a first transmission line, and a second die, comprising a second transmission line. Each die includes a first face and an opposing second face, and the second die is stacked above the first die so that the first face of the second die is coupled to the second face of the first die. The electronic assembly further includes a first conductive pathway between one end of the first transmission line and a first connection point at the first face of the first die, a second conductive pathway between one end of the second transmission line and a second connection point at the first face of the first die, and a third conductive pathway between the other ends of the first and second transmission lines.

Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

Abstract: Methods for providing fill patterns for IC devices are disclosed. An example method includes detecting a first device and a second device in an image, e.g., a two- or three-dimensional image representing the IC device. A line is defined based on the devices. The line divides the image into a first section and a second section. A first structure is generated based on the first device. A second structure is generated based on the second device. The second structure is a mirror image of the first structure across the line. A first fill pattern is generated in the first section based on the first structure. A second fill pattern is generated in the second section based on the first fill pattern, e.g., through a reflection transformation of the first fill pattern across the line. The two fill patterns represent patterns of fill structures to be included in the IC device.