Patents by Inventor Peter Blais

Peter Blais has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240237220
    Abstract: An improved circuit board core material, and method of making the circuit board core material, is provided wherein the circuit board core material is particularly suitable for use in a circuit board. The circuit board core material comprises a laminate. The laminate comprises a prepreg layer with a first clad layer on the prepreg layer wherein the prepreg layer comprises a pocket. An electronic component is in the pocket wherein the electronic component comprises a first external termination and a second external termination. The first external termination is laminated to, and in electrical contact with, the first clad layer and said second external termination is in electrical contact with a conductor.
    Type: Application
    Filed: March 25, 2024
    Publication date: July 11, 2024
    Inventors: Brandon Summey, Peter Blais, Robert Ramsbottom, Jeffrey Poltorak, Courtney Elliott
  • Patent number: 11943869
    Abstract: An improved circuit board core material, and method of making the circuit board core material, is provided wherein the circuit board core material is particularly suitable for use in a circuit board. The circuit board core material comprises a laminate. The laminate comprises a prepreg layer with a first clad layer on the prepreg layer wherein the prepreg layer comprises a pocket. An electronic component is in the pocket wherein the electronic component comprises a first external termination and a second external termination. The first external termination is laminated to, and in electrical contact with, the first clad layer and said second external termination is in electrical contact with a conductor.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: March 26, 2024
    Assignee: KEMET Electronics Corporation
    Inventors: Brandon Summey, Peter A. Blais, Robert Andrew Ramsbottom, Jeffrey Poltorak, Courtney Elliott
  • Patent number: 11893839
    Abstract: A performance system can enable an untrained end user to analyze the performance of a vehicle based on performance data that the vehicle's ECU generates. The performance system can include a performance tool that is configured to request performance data from one or more ECUs of a vehicle. The performance system can also include a performance engine that interfaces with the performance tool to create a log of the performance data. The performance engine can be configured to process the performance data log to generate a number of performance values which correspond to performance parameters. The performance engine can then use the performance values to generate performance representations which can then be presented to the end user.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: February 6, 2024
    Assignee: Integrated Engineering LLC
    Inventors: Peter Blais, David Blais
  • Publication number: 20230276574
    Abstract: An improved circuit board core material, and method of making the circuit board core material, is provided wherein the circuit board core material is particularly suitable for use in a circuit board. The circuit board core material comprises a laminate. The laminate comprises a prepreg layer with a first clad layer on the prepreg layer wherein the prepreg layer comprises a pocket. An electronic component is in the pocket wherein the electronic component comprises a first external termination and a second external termination. The first external termination is laminated to, and in electrical contact with, the first clad layer and said second external termination is in electrical contact with a conductor.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 31, 2023
    Inventors: Brandon Summey, Peter A. Blais, Robert Andrew Ramsbottom, Jeffrey Poltorak, Courtney Elliott
  • Patent number: 11655927
    Abstract: An expandable pipe seal includes a sleeve that is expandable from a first, compact configuration to a second, expanded configuration having a larger outer diameter than the first configuration. The sleeve may be formed from sheet material that is rolled into a cylindrical shape such that a first longitudinal edge of the sheet overlaps a second longitudinal edge of the sheet in a circumferential direction. The sleeve is provided with first and second locking structures that cooperate to facilitate expansion of the sleeve from the first configuration to the second configuration and, thereafter, maintain the sleeve in the expanded configuration. The pipe seal includes sealing structure disposed on an outer surface of the sleeve, and which is compressed against the inner wall of a pipe to be repaired in the second configuration of the sleeve.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: May 23, 2023
    Assignee: HydraTech Engineered Products, LLC
    Inventors: Peter Blais, Michael Fox
  • Publication number: 20220397223
    Abstract: An expandable pipe seal includes a sleeve that is expandable from a first, compact configuration to a second, expanded configuration having a larger outer diameter than the first configuration. The sleeve may be formed from sheet material that is rolled into a cylindrical shape such that a first longitudinal edge of the sheet overlaps a second longitudinal edge of the sheet in a circumferential direction. The sleeve is provided with first and second locking structures that cooperate to facilitate expansion of the sleeve from the first configuration to the second configuration and, thereafter, maintain the sleeve in the expanded configuration. The pipe seal includes sealing structure disposed on an outer surface of the sleeve, and which is compressed against the inner wall of a pipe to be repaired in the second configuration of the sleeve.
    Type: Application
    Filed: June 14, 2021
    Publication date: December 15, 2022
    Inventors: Peter Blais, Michael Fox
  • Publication number: 20220375280
    Abstract: A performance system can enable an untrained end user to analyze the performance of a vehicle based on performance data that the vehicle's ECU generates. The performance system can include a performance tool that is configured to request performance data from one or more ECUs of a vehicle. The performance system can also include a performance engine that interfaces with the performance tool to create a log of the performance data. The performance engine can be configured to process the performance data log to generate a number of performance values which correspond to performance parameters. The performance engine can then use the performance values to generate performance representations which can then be presented to the end user.
    Type: Application
    Filed: May 21, 2021
    Publication date: November 24, 2022
    Inventors: Peter Blais, David Blais
  • Publication number: 20210243897
    Abstract: An improved circuit board core material, and method of making the circuit board core material, is provided wherein the circuit board core material is particularly suitable for use in a circuit board. The circuit board core material comprises a laminate. The laminate comprises a prepreg layer with a first clad layer on the prepreg layer wherein the prepreg layer comprises a pocket. An electronic component is in the pocket wherein the electronic component comprises a first external termination and a second external termination. The first external termination is laminated to, and in electrical contact with, the first clad layer and said second external termination is in electrical contact with a conductor.
    Type: Application
    Filed: February 1, 2021
    Publication date: August 5, 2021
    Inventors: Brandon Summey, Peter A. Blais, Robert Andrew Ramsbottom, Jeffrey Poltorak, Courtney Elliott
  • Patent number: 10283276
    Abstract: An improved array of capacitors is provided wherein the improvement includes improved electrical properties and improved packing density. The array has an anode foil and a dielectric on a surface of the anode foil. A multiplicity of areas are defined on the dielectric wherein each area is circumvented by an isolation material and the isolation material extends through the dielectric. A conductive cathode layer in each area forms a capacitive couple. At least one substrate vacancy is in the anode foil and the substrate vacancy electrically isolates adjacent anodes of adjacent capacitive couples. A carrier film is attached to the capacitive couples.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: May 7, 2019
    Assignee: KEMET Electronics Corporation
    Inventors: Brandon Summey, Peter Blais, Yanming Liu
  • Patent number: 9741494
    Abstract: An improved array of capacitors is provided wherein the improvement includes improved electrical properties and improved packing density. The array has an anode foil and a dielectric on a surface of the anode foil. A multiplicity of areas are defined on the dielectric wherein each area is circumvented by an isolation material and the isolation material extends through the dielectric. A conductive cathode layer in each area forms a capacitive couple. At least one substrate vacancy is in the anode foil and the substrate vacancy electrically isolates adjacent anodes of adjacent capacitive couples. A carrier film is attached to the capacitive couples.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: August 22, 2017
    Assignee: KEMET Electronics Corporation
    Inventors: Brandon Summey, Peter Blais, Yanming Liu
  • Publication number: 20170178818
    Abstract: An improved array of capacitors is provided wherein the improvement includes improved electrical properties and improved packing density. The array has an anode foil and a dielectric on a surface of the anode foil. A multiplicity of areas are defined on the dielectric wherein each area is circumvented by an isolation material and the isolation material extends through the dielectric. A conductive cathode layer in each area forms a capacitive couple. At least one substrate vacancy is in the anode foil and the substrate vacancy electrically isolates adjacent anodes of adjacent capacitive couples. A carrier film is attached to the capacitive couples.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 22, 2017
    Inventors: Brandon Summey, Peter Blais, Yanming Liu
  • Publication number: 20140226258
    Abstract: An improved array of capacitors is provided wherein the improvement includes improved electrical properties and improved packing density. The array has an anode foil and a dielectric on a surface of the anode foil. A multiplicity of areas are defined on the dielectric wherein each area is circumvented by an isolation material and the isolation material extends through the dielectric. A conductive cathode layer in each area forms a capacitive couple. At least one substrate vacancy is in the anode foil and the substrate vacancy electrically isolates adjacent anodes of adjacent capacitive couples. A carrier film is attached to the capacitive couples.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 14, 2014
    Inventors: Brandon Summey, Peter Blais, Yanming Liu
  • Patent number: 8125766
    Abstract: A capacitor assembly with a substrate having a first face and a second face. A multiplicity of capacitors are mounted on the first face wherein each capacitor has a first lead and a second lead of opposite polarity to the first lead. A bridge is in electrical contact with multiple first leads. A tree is in electrical contact with the bridge wherein the tree passes through a via of the substrate and is in electrical contact with a first trace of the second face. A second trace is on the second face wherein the second lead is in electrical contact with the second trace.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: February 28, 2012
    Assignee: Kemet Electronics Corporation
    Inventors: John D. Prymak, Peter Blais, George Haddox, Michael Prevallet, Jim Piller, Chris Stolarski, Chris Wayne
  • Publication number: 20090310280
    Abstract: A capacitor assembly with a substrate having a first face and a second face. A multiplicity of capacitors are mounted on the first face wherein each capacitor has a first lead and a second lead of opposite polarity to the first lead. A bridge is in electrical contact with multiple first leads. A tree is in electrical contact with the bridge wherein the tree passes through a via of the substrate and is in electrical contact with a first trace of the second face. A second trace is on the second face wherein the second lead is in electrical contact with the second trace.
    Type: Application
    Filed: June 13, 2008
    Publication date: December 17, 2009
    Inventors: John D. Prymak, Peter Blais, George Haddox, Michael Prevallet, Jim Piller, Chris Stolarski, Chris Wayne
  • Publication number: 20080123251
    Abstract: A process for forming a capacitive couple. The process includes forming a highly porous body of a conducting material with interior struts and voids in electrical contact. A dielectric layer is formed in the voids on the struts with a material having a dielectric constant above 100. An insulating layer is formed on the struts not covered by the dielectric layer. A conductive layer is formed on the dielectric layer and on the insulating layer.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 29, 2008
    Inventors: Michael S. Randall, Peter Blais, Pascal Pinceloup, Daniel J. Skamser, Abhijit Gurav, Azizuddin Tajuddin, John T. Kinard, Philip Lessner
  • Patent number: 7280342
    Abstract: A low inductance multi-layer capacitor. The capacitor comprises interleaved parallel internal electrode plates with dielectric there between. Each internal electrode plate comprises two lead-out tabs and is generally T shaped. A first external electrode terminal is electrically connected to the lead-out tabs of the even internal electrode plates, and a second external electrode terminal is electrically connected to the lead-out tabs of the odd internal electrode plates. The external electrode terminals are on a common first exterior surface and a common opposing second exterior surface of the capacitor.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: October 9, 2007
    Assignee: Kemet Electronics Corporation
    Inventors: Michael S. Randall, Allen Hill, Peter Blais, Garry Renner, Randal Vaughan, Azizuddin Tajuddin
  • Publication number: 20070165361
    Abstract: A low inductance multi-layer capacitor. The capacitor comprises interleaved parallel internal electrode plates with dielectric there between. Each internal electrode plate comprises two lead-out tabs and is generally T shaped. A first external electrode terminal is electrically connected to the lead-out tabs of the even internal electrode plates, and a second external electrode terminal is electrically connected to the lead-out tabs of the odd internal electrode plates. The external electrode terminals are on a common first exterior surface and a common opposing second exterior surface of the capacitor.
    Type: Application
    Filed: December 15, 2006
    Publication date: July 19, 2007
    Inventors: Michael S. Randall, Allen Hill, Peter Blais, Garry Renner, Randal Vaughan, Azizuddin Tajuddin