Low inductance high ESR capacitor
A low inductance multi-layer capacitor. The capacitor comprises interleaved parallel internal electrode plates with dielectric there between. Each internal electrode plate comprises two lead-out tabs and is generally T shaped. A first external electrode terminal is electrically connected to the lead-out tabs of the even internal electrode plates, and a second external electrode terminal is electrically connected to the lead-out tabs of the odd internal electrode plates. The external electrode terminals are on a common first exterior surface and a common opposing second exterior surface of the capacitor.
This application is a continuation-in-part of U.S. patent Ser. No. 11/334,271, filed Jan. 18, 2006 (attorney docket number 31433/142) which is now pending and incorporated by reference.
BACKGROUNDThe present invention is related to a low inductance capacitor having two terminals. More particularly, the present invention is related to a low inductance multi-layer capacitor having two terminals which electrically connect to the lead-out tabs of interleaved T shaped electrodes.
In summary, the art has been seeking a low inductance multi-layer capacitor for use in high frequency decoupling applications which is effective and inexpensive to manufacture, as well as simple to use. Recent developments in microprocessors and memory technologies have led to an increased demand for faster switching speeds and greater densities in integrated circuits. Because of these demands, higher operating frequencies or switching speeds are required which cause larger current fluctuations and difficulties in controlling voltage fluctuations accompanying these larger current fluctuations. Today, sophisticated noise filtering techniques are necessary to stabilize these fluctuations.
Decoupling capacitors are often used as a means of overcoming physical and time constraints found in integrated circuits by reducing voltage fluctuations and enhancing the reliability of the device. Commonly, multi-layer ceramic capacitors are used as decoupling capacitors because of their size, availability, density, performance, reliability, and cost. Decoupling capacitors are usually mounted on a printed circuit board (“PCB”) in close proximity to the decoupled microprocessor or integrated circuit. By supplying quick charge flow at the event of a high speed transient current fluctuation, the decoupling capacitor supplies a supplemental current, thereby reducing voltage fluctuation of the power source.
As switching speeds and device densities of integrated circuits increase, greater demands are placed on decoupling capacitors. In the past, this demand has been met through the use of larger and larger capacitance value capacitors. The use of larger value capacitors, however, creates two problems. First, there is an ongoing demand for smaller and smaller devices due to the ongoing desire for the miniaturization of electronic apparatuses. Second, the larger the capacitor size, the larger the parasitic inductance becomes. Parasitic inductance is almost always undesirable because it degrades the effectiveness of the capacitor. Capacitors with large parasitic inductances have relatively low resonance frequency combined with relatively high impedance at high frequencies making them unusable for many high-speed applications. The relationship between resonance frequency and capacitance can be expressed in the following equation:
wherein fo represents resonance frequency, L represents parasitic inductance, which is suitably estimated as equivalent series inductance (“ESL”), and C represents capacitance. As can be seen, the smaller the inductance L, the higher the resonance frequency fo becomes.
Mutual inductance is also undesirable in an electric circuit because it causes unwanted coupling between conductors in a circuit. Mutual inductance is the property of an electric circuit or component which generates an electromotive force (“EMF”). Mutual inductance occurs as a result of a change in the current flowing through a neighboring circuit with which it is magnetically linked. In other words, mutual inductance is the voltage induced in one circuit when the current in another circuit changes by a unit amount in unit time. The EMF generated by the presence of mutual inductance maintains a direction which is always opposite the change in the magnetic field.
Low inductance capacitors are known in the art. U.S. Pat. No. 6,950,300 to Sutardja (“the '300 patent”) discloses a multilayer capacitor having a low parasitic inductance. A sideways T shaped electrode is vertically oriented and mounted to a PCB. The T extensions are electrically connected to four separate external contact bars at the bottom and top of the capacitor. The distance between the two external contact bars at the top and bottom of the capacitor is reduced to decrease the parasitic inductance. While the '300 patent discloses a capacitor with lower parasitic inductance than standard multilayer capacitors, it does not disclose a capacitor with lower mutual inductance. Furthermore, the '300 patent still maintains a high parasitic inductance due to the limiting surface area of the terminations. The capacitors disclosed in the '300 patent are expensive to manufacture and have limiting mounting capabilities due to the use of separate external contact bar terminations. Furthermore, the external electrodes are only internally connected to the capacitor body.
U.S. Pat. No. 6,496,355 to Galvagni et al. (“the '355 patent”) discloses an improved low inductance interdigitated capacitor and corresponding termination scheme. The '355 patent discloses the use of solder stops to create a ball limiting metallurgy and provides for the use of electrode tabs extending from electrode layers which are exposed on the sides of the capacitor body. While the '355 patent provides for a lower parasitic and mutual inductance, both the parasitic and mutual inductance remain high because of the electrode configuration and orientation. Further, the '355 patent requires the use of solder stops and maintains limiting mounting capabilities.
U.S. Pat. No. 7,054,136 to Ritter et al. (“the '136 patent”) discloses a multilayer ceramic capacitor assembly capable of exhibiting low high-frequency inductance and a controlled ESR. The '136 patent teaches multi-layered termination wherein the multiple layers reduce thermal shock problems in the capacitor. The use of a serpentine design electrode element is also disclosed to enhance the ESR. The serpentine pattern disclosed in the '136 patent does not effectively reduce ESR because each electrode plate has a wide surface area when the current enters each electrode plate from the termination. Further, the capacitor has a high inductance due to, for example, the electrode configuration and the current passing through multiple faces on the capacitor.
Further multilayer capacitors also known in the art include U.S. Pat. No. 6,292,351 to Ahiko et al., and U.S. Pat. Nos. 6,956,730; 6,965,507; and 6,765,781 and U.S. Publication Nos. 2006/0028785 and 2005/0264977 all to Togashi. These patents do not disclose capacitors with low mutual inductance and provide for capacitors with high parasitic inductance due to the limiting surface area of the interdigitated external terminations. Moreover, the items described in these patents are expensive to manufacture because of the lack of symmetry of the internal electrodes and the limiting mounting capabilities due to the use of separate external contact bar terminations.
In summary, the art has been seeking a multi-layer capacitor which generates low parasitic and mutual inductance in decoupling applications, is compatible with most existing circuit boards, maintains electrode symmetry and which is easily mountable and inexpensive to manufacture.
SUMMARY OF THE INVENTIONIt is an object of the present invention to provide a capacitor which eliminates or lowers mutual inductance.
It is another object of the present invention to provide a capacitor which has low parasitic inductance.
It is another object of the present invention to provide a capacitor which has increased effective equivalent series resistance (ESR).
It is yet another object of the present invention to provide a capacitor which has inherently lower equivalent series inductance (ESL) and can therefore be used in high frequency decoupling applications.
An advantage of the present invention is the simplicity of manufacture since the internal electrodes can be manufactured in a manner similar to prior art capacitors.
Another advantage of the present invention is the ease of use and versatile mounting capabilities relative to common interdigitated capacitors because it does not require any change in the design of the circuit board.
Yet another advantage of the present invention is the ability to both internally and externally connect the external electrode terminals to the capacitor body
These and other advantages are provided in the capacitor of the present invention. In a particularly preferred embodiment, the capacitor comprises first internal electrode plates and second internal electrode plates which are arranged parallel to each other with dielectric there between. The first internal electrode plates comprise opposing first and second lead-out tabs, a first land, and a first planar element. The first and second lead-out tabs have a combined length greater than the length of the first planar element. Similarly, the second internal electrode plates comprise opposing third and fourth lead-out tabs, a second land, and a second planar element. The third and fourth lead-out tabs have a combined length greater than the length of the second planar element. A first external electrode terminal is electrically connected to the first internal electrode plates by the first and second lead-out tabs, and a second external electrode terminal is electrically connected to the second internal electrode plates by the opposing third and fourth lead-out tabs. Further, the first and second external electrode terminals are on a common first exterior surface and a common opposing second exterior surface of the capacitor.
In another particularly preferred embodiment, the capacitor comprises more than one interleaved internal electrode plate wherein each internal electrode plate is arranged spaced apart in parallel with dielectric there between. Each internal electrode plate comprises a first and second lead-out tab, a land, and a planar element. The first and second lead-out tab have a combined length greater than the length of the planar element. A first external electrode terminal is electrically connected to the first and second lead-out tab of even ones of the internal electrode plates, and a second external electrode terminal is electrically connected to the first and second lead-out tab of odd ones of the internal electrode plates. Both the first external electrode terminal and said second external electrode terminal are each arranged on a common first exterior surface, a common opposing exterior surface, and a perpendicular face between the first exterior surface and the opposing exterior surface of the capacitor.
The invention will be described with reference to the accompanying drawings forming an integral part of the present disclosure. In various drawings, similar elements will be numbered accordingly.
A low inductance multilayer capacitor having generally ‘T’ shaped interleaved internal electrodes and two external electrode terminals is disclosed. A low inductance multilayer capacitor having generally ‘T’ shaped interleaved internal electrodes is also disclosed in U.S. application Ser. No. 11/334,271 which is incorporated in its entirety herein.
In a finished capacitor, multiple overlaid internal electrodes would be arranged in a stacked relationship with dielectric between each internal electrode and its nearest neighbor(s). Each first internal electrode would be electrically connected to a common external electrode. Similarly, each overlaid second internal electrode would be electrically connected to a second common external electrode. As would be realized to one of ordinary skill in the art, the internal electrodes are in a stacked relationship with each internal electrode having opposite polarity to each adjacent internal electrode.
The first lead-out tabs, 28 and 28′, comprise a first contact face, 32 and 32′, which will be on a common face of the capacitor. The second lead-out tabs, 30 and 30′, comprise a second contact face, 34 and 34′, also on a common face of the capacitor. The contact faces are not encased and extend beyond the dielectric material to connect the internal electrode plates to the external electrode terminals. For example, referring back to
The lead-out tabs can have either linear or non-linear side edges. In a particularly preferred embodiment, as shown, the side edges are linear and extend at approximately a ninety degree angle from the contact faces. A primary advantage to this embodiment is the simplicity of manufacture. In another embodiment, the side edges of the lead-out tabs are linear and diverge outward from the contact faces creating a generally trapezoidal shape. In yet another embodiment, the side edges of the lead-out tabs are non-linear and radial. Any lead-out tab shape is suitable for demonstration of the present invention as long as the generally ‘T’ shape is maintained yet complicated functions are not necessary and merely add manufacturing complexity. Some complexity to the generally ‘T’ shape as discussed below and illustrated in
The first lead-out tabs, 128 and 128′, comprise a first contact face, 132 and 132′, which will be on a common face of the capacitor. The second lead-out tabs, 130 and 130′, comprise a second contact face, 134 and 134′, also on a common face of the capacitor. The contact faces are not encased and extend beyond the dielectric material to connect the internal electrode plates to the external electrode terminals. For example, referring to
Similar to
The first lead-out tabs, 228 and 228′, comprise a first contact face, 232 and 232′, which will be on a common face of the capacitor. The second lead-out tabs, 230 and 230′, comprise a second contact face, 234 and 234′, also on a common face of the capacitor. The contact faces are not encased and extend beyond the dielectric material to connect the internal electrode plates to the external electrode terminals. For example, referring to
The lead-out tabs of the embodiment shown in
The entire capacitor, except for the contact faces of the internal electrode plate lead-out tabs, may be encased in an insulating material. The insulating material is nonconductive and forms an envelope that electrical charge can neither enter nor escape except through the external electrodes under normal operating conditions. In one particularly preferred embodiment, the insulating material is a dielectric material such as a ceramic.
The present invention is a two external electrode terminal design. In general, each external electrode terminal at least partially covers at least three sides of a capacitor body. The internal electrode plates are electrically connected to the external electrode terminals on at least two common sides. The two external electrode terminal design is especially advantageous over common interdigitated capacitors because the surface area of the external electrode terminal is large and covers at least three sides of the capacitor body which allows the current to flow into a greater area resulting in a lower inductance. Furthermore, the two external electrode terminals can be arranged at a minimal distance from each other to even further minimize parasitic inductance and minimize stress fractures of the capacitor. A two terminal design is also an industry standard for surface mount capacitor technology, which simplifies design and manufacturing costs considerably.
An embodiment of the present invention is provided in
In a preferred embodiment, the internal electrode plate lands, 27 and 27′, are not electrically connected to the external electrode terminals, 42 and 44, at the perpendicular faces, 50, 52, 54, and 56. So that the internal electrode plate lands, 27 and 27′, are not electrically connected to the external electrode terminals, 42 and 44, an insulating material, such as a dielectric, may be positioned between the internal electrode plate lands, 27 and 27′, and the external electrode terminals, 42 and 44. This embodiment is preferred because it allows both internal and external connection of the external electrode terminals to the capacitor body. Internal Electrode plate lands 127, 127′, 227, and 227′ are optionally also not electrically connected to the external electrode terminals as discussed above with respect to lands 27 and 27′.
Another particularly preferred embodiment of the present invention is provided in
In a preferred embodiment, the internal electrode plate lands, 27 and 27′, are not electrically connected to the external electrode terminals, 62 and 64 at the perpendicular faces, 70, 72, 74, and 76. So that the internal electrode plate lands, 27 and 27′, are not electrically connected to the external electrode terminals, 62 and 64, an insulating material, such as a dielectric, may be positioned between the internal electrode plates, 12 and 12′, and external electrodes terminals, 62 and 64. This embodiment is preferred because it allows both internal and external connection of the external electrode terminals to the capacitor body. Internal Electrode plate lands 127, 127′, 227, and 227′ are optionally also not electrically connected to the external electrode terminals as discussed above with respect to lands 27 and 27′. The embodiment illustrated in
In the embodiment illustrated in
The invention has been described with particular emphasis on the preferred embodiments without limit thereto. Based on the foregoing description, other embodiments and alterations would be apparent without departing from the scope of the invention which is more specifically set forth in the claims appended hereto.
Claims
1. A capacitor comprising:
- first internal electrode plates;
- second internal electrode plates arranged parallel to said first internal electrode plates with dielectric between;
- wherein said first internal electrode plates comprise a first and second lead-out tab, a first land, and a first planar element, wherein said first and second lead-out tab have a first combined length greater than a first length of said first planar element;
- wherein said second internal electrode plates comprise an opposing third and fourth lead-out tab, a second land, and a second planar element, wherein said third and fourth lead-out tab have a second combined length greater than a second length of said second planar element;
- a first external electrode terminal electrically connected to said first internal electrode plates by said first and second lead-out tab;
- a second external electrode terminal electrically connected to said second internal electrode plates by said opposing third and fourth lead-out tab; and
- wherein said first external electrode terminal and said second external electrode terminal are on a common first exterior surface and a common opposing second exterior surface of the capacitor.
2. The capacitor of claim 1 wherein said first combined length and said second combined length are the same.
3. The capacitor of claim 1 wherein said first length of said first planar element is the same as said second length of said second planar element.
4. The capacitor of claim 1 wherein said first internal electrode plate is symmetrical to said second internal electrode plate.
5. The capacitor of claim 1 wherein said first and second external electrode terminals are not electrically connected to said first and second internal electrode plate by said first and second land, respectively.
6. The capacitor of claim 1 wherein said first external electrode terminal and said second external electrode terminal are on a common third exterior surface and a common fourth exterior surface of the capacitor.
7. The capacitor of claim 1 wherein when said first and second external terminals are connected to a substrate.
8. The capacitor of claim 7 wherein said first and second internal electrode plates of said capacitor are oriented perpendicular to said substrate.
9. The capacitor of claim 7 wherein said first and second internal electrode plates of said capacitor are oriented parallel to said substrate.
10. The capacitor or claim 1 wherein said first internal electrode plates are offset to said second internal electrode plates such that said first end does not extend to said second land and said second end does not extend to said first land.
11. The capacitor of claim 10 wherein at least one first via electrically connects said first external electrode terminal to said first internal electrode plates.
12. The capacitor of claim 11 wherein at least one second via electrically connects said second external electrode terminal to said second internal electrode plates.
13. The capacitor of claim 1 wherein said first internal electrode plate forms a generally ‘T’ shape.
14. The capacitor of claim 1 wherein said first and second lead-out tab form a serpentine pattern.
15. The capacitor of claim 1 wherein a first width of said first and second lead-out tab is less than a second width of said first planar element.
16. The capacitor of claim 15 wherein a third width of said third and fourth lead-out tab is less than a fourth width of said second planar element.
17. A capacitor comprising:
- m interleaved internal electrode plates;
- wherein each internal electrode plate of said m internal electrode plates are arranged spaced apart in parallel with dielectric between;
- wherein m is an integer greater than 1;
- wherein each said internal electrode plate comprises a first and second lead-out tab, a land, and a planar element, wherein said first and second lead-out tab have a combined length greater than a length of said planar element;
- a first external electrode terminal electrically connected to said first and second lead-out tab of even ones of said m internal electrode plates;
- a second external electrode terminal electrically connected to said first and second lead-out tab of odd ones of said m internal electrode plates; and
- wherein said first external electrode terminal and said second external electrode terminal are each arranged on a common first exterior surface, a common opposing exterior surface, and a perpendicular face between said first exterior surface and said opposing exterior surface of the capacitor.
18. The capacitor of claim 17 wherein said first external electrode terminal and said second external electrode terminal are not electrically connected to said m internal electrode plates by said lands.
19. The capacitor of claim 17 wherein said first external electrode terminal and said second external electrode terminal are on a common first perpendicular face and a common second perpendicular face between said first exterior surface and said opposing exterior surface of the capacitor.
20. The capacitor of claim 17 wherein said first external electrode terminal and said second external electrode terminal are connected to a substrate.
21. The capacitor of claim 20 wherein said m internal electrode plates of said capacitor are oriented perpendicular to the substrate.
22. The capacitor of claim 20 wherein said m internal electrode plates of said capacitor are oriented parallel to said substrate.
23. The capacitor or claim 17 wherein said m internal electrode plates are offset such that said ends of said even ones of said m electrode plates do not extend to said lands of said odd ones of said m electrode plates and said ends of said odd ones of said m electrode plates do not extend to said lands of said even ones of said m electrode plates.
24. The capacitor of claim 23 wherein at least one first via electrically connects said first external electrode terminal to said even ones of said m internal electrode plates.
25. The capacitor of claim 24 wherein at least one second via electrically connects said second external electrode terminal to said odd ones of said m internal electrode plates.
26. The capacitor of claim 17 wherein said first internal electrode plate forms a generally ‘T’ shape.
27. The capacitor of claim 17 wherein said first and second lead-out tab form a serpentine pattern.
Type: Application
Filed: Dec 15, 2006
Publication Date: Jul 19, 2007
Inventors: Michael S. Randall (Simpsonville, SC), Allen Hill (Simpsonville, SC), Peter Blais (Milford, MA), Garry Renner (Easley, SC), Randal Vaughan (Fountain Inn, SC), Azizuddin Tajuddin (Laurens, SC)
Application Number: 11/639,796
International Classification: H01G 4/228 (20060101);