Patents by Inventor Peter Cirigliano
Peter Cirigliano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070075038Abstract: A method for etching features in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have irregular profiles along depths of the photoresist features. The irregular profiles along the depths of the photoresist features of the sidewalls of the photoresist features are corrected comprising at least one cycle, where each cycle comprises a sidewall deposition phase and a profile shaping phase. Feature is etched into the etch layer through the photoresist features. The mask is removed.Type: ApplicationFiled: October 5, 2005Publication date: April 5, 2007Inventors: S.M. Sadjadi, Peter Cirigliano, Jisoo Kim, Zhisong Huang, Eric Hudson
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Publication number: 20060266478Abstract: A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.Type: ApplicationFiled: May 31, 2005Publication date: November 30, 2006Inventors: Sangheon Lee, Dae-Han Choi, Jisoo Kim, Peter Cirigliano, Zhisong Huang, Robert Charatan, S.M. Reza Sadjadi
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Publication number: 20060194439Abstract: A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.Type: ApplicationFiled: September 9, 2005Publication date: August 31, 2006Inventors: S.M. Sadjadi, Peter Cirigliano, Ji Kim, Zhisong Huang, Eric Hudson
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Publication number: 20060162657Abstract: A confinement assembly for a semiconductor processing chamber is provided. The confinement assembly includes a plurality of confinement rings disposed over each other. Each of the plurality of confinement rings are separated by a space and each of the plurality of confinement rings have a plurality of holes defined therein. A plunger extending through aligned holes of corresponding confinement rings is provided. The plunger is moveable in a plane substantially orthogonal to the confinement rings. A proportional adjustment support is affixed to the plunger. The proportional adjustment support is configured to support the confinement rings, such that as the plunger moves in the plane, the space separating each of the plurality of confinement rings is proportionally adjusted. In one embodiment the proportional adjustment support is a bellows sleeve. A semiconductor processing chamber and a method for confining a plasma in an etch chamber having a plurality of confinement rings are provided.Type: ApplicationFiled: January 27, 2005Publication date: July 27, 2006Inventor: Peter Cirigliano
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Publication number: 20060024968Abstract: A method of forming a feature in a low-k (k<3.0) dielectric layer is provided. A low-k dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the low-k dielectric layer. At least one feature is etched into the low-k dielectric layer. A stripping gas comprising CO2 is provided. A plasma is formed from the stripping gas comprising CO2. The plasma from the stripping gas comprising CO2 is used to strip the patterned photoresist mask.Type: ApplicationFiled: August 2, 2004Publication date: February 2, 2006Inventors: Eric Hudson, Peter Cirigliano
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Patent number: 6909195Abstract: The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.Type: GrantFiled: April 16, 2004Date of Patent: June 21, 2005Assignee: Lam Research CorporationInventors: SiYi Li, S. M. Reza Sadjadi, David R. Pirkle, Steve Lassig, Sean Kang, Vinay Pohray, Peter Cirigliano
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Publication number: 20050009324Abstract: The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.Type: ApplicationFiled: April 16, 2004Publication date: January 13, 2005Applicant: Lam Research CorporationInventors: SiYi Li, S.M. Sadjadi, David Pirkle, Stephan Lassig, Sean Kang, Vinay Pohray, Peter Cirigliano
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Publication number: 20040224520Abstract: A method for etching a feature in a low-k dielectric layer through a photoresist etch mask over a substrate. A gas-modulated cyclic stripping process is performed for more than three cycles for stripping a single photoresist mask. Each cycle of the gas-modulated cyclic stripping process comprises performing a protective layer formation phase and a stripping phase. The protective layer forming phase using first gas chemistry with a deposition gas chemistry, wherein the protective layer forming phase is performed in about 0.005 to 10 seconds for each cycle. The performing the stripping phase for stripping the photoresist mask using a second gas chemistry using a stripping gas chemistry, where the first gas chemistry is different than the second gas chemistry, wherein the etching phase is performed in about 0.005 to 10 seconds for each cycle.Type: ApplicationFiled: June 3, 2004Publication date: November 11, 2004Applicant: Lam Research CorporationInventors: Seokmin Yun, Ji Zhu, Peter Cirigliano, Sangheon Lee, Thomas S. Choi, Peter Loewenhardt, Mark H. Wilcoxson, Reza Sadjadi, Eric A. Hudson, James V. Tietz
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Patent number: 6794293Abstract: The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.Type: GrantFiled: October 5, 2001Date of Patent: September 21, 2004Assignee: Lam Research CorporationInventors: SiYi Li, S. M. Reza Sadjadi, David R. Pirkle, Steve Lassig, Sean Kang, Vinay Pohray, Peter Cirigliano
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Patent number: 6780569Abstract: A method for creating semiconductor devices is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. Polymers in the patterned photoresist layer are chemically cross-linked by exposure to at least one reactive chemical. The pattern in the photoresist layer is transferred to the wafer. A reaction chamber for processing a wafer with a patterned layer of photoresist material, wherein the photoresist material was patterned by exposing the photoresist material using light of a wavelength less than 248 nm is provided. A chamber is provided with a central cavity. A wafer support for supporting the wafer in the central cavity is provided. A cross-linking reactive chemical source in fluid contact with the chamber and which provides a reactive chemical which causes cross-linking of the photoresist is provided.Type: GrantFiled: February 4, 2002Date of Patent: August 24, 2004Assignee: Lam Research CorporationInventors: Eric Hudson, Reza Sadjadi, Daxing Ren, Wan-Lin Chen, Douglas Keil, Peter Cirigliano
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Publication number: 20040038540Abstract: The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.Type: ApplicationFiled: October 5, 2001Publication date: February 26, 2004Applicant: Lam Research CorporationInventors: SiYi Li, S.M. Reza Sadjadi, David R. Pirkle, Stephan Lassig, Sean Kang, Vinay Pohray, Peter Cirigliano