Abstract: A method for manufacturing a dynamic random access memory device includes providing a semiconductor substrate and forming a highly doped diffusion region in a surface of the semiconductor substrate. A wordline structure is then deposited on the surface of the semiconductor substrate, where the wordline structure includes an electrically conductive gate layer. An opening is further formed in the wordline structure, where the opening is located at a first end of and extending to the highly doped diffusion region. A semiconductor pillar is then formed in the opening by selective epitaxial growth. An end of the semiconductor pillar is then doped and the doped end is connected with a memory element.

Abstract: A magnetic memory structure that includes a two-terminal resistive memory element electrically connected with a selector structure. The selector structure includes a semiconductor pillar structure formed on a semiconductor substrate. The selector structure is surrounded by a gate dielectric layer, and the semiconductor pillar structure and gate dielectric layer are surrounded by an electrically conductive gate structure. The semiconductor pillar has first and second dimensions in a plane parallel with the surface of the semiconductor substrate that are unequal with one another. The semiconductor pillar structure can have a cross-section parallel with the semiconductor substrate surface that is in the shape of a: rectangle; oval elongated polygon, etc. The length of the longer dimension can be adjusted to provide a desired amount of current though the semiconductor pillar structure to drive the two-terminal resistive memory element.

Abstract: A vertical transistor structure having a metal gate wordline. The vertical transistor structure can include an epitaxially grown semiconductor column surrounded by a thin gate dielectric layer. A gate structure can surround the semiconductor column and the gate dielectric layer. The device can include first and second dielectric layers and an electrically conductive metal layer located between the first and second dielectric layers. The electrically conductive metal of the gate structure can be tungsten (W). In addition, a thin layer of Ti or TiN can be formed between the metal gate layer and the first and second dielectric layers and the gate dielectric layer. The metal gate layer can be formed with or without the use of a sacrificial layer.

Abstract: A method for manufacturing a dynamic random access memory device includes providing a semiconductor substrate and forming a highly doped diffusion region in a surface of the semiconductor substrate. A wordline structure is then deposited on the surface of the semiconductor substrate, where the wordline structure includes an electrically conductive gate layer. An opening is further formed in the wordline structure, where the opening is located at a first end of and extending to the highly doped diffusion region. A semiconductor pillar is then formed in the opening by selective epitaxial growth. An end of the semiconductor pillar is then doped and the doped end is connected with a memory element.

Abstract: A DRAM memory cell and memory cell array incorporating a metal silicide bit line buried within a doped portion of a semiconductor substrate and a vertical semiconductor structure electrically connected with a memory element such as a capacitive memory element. The buried metal silicide layer functions as a bit buried bit line which can provide a bit line voltage to the capacitive memory element via the vertical transistor structure. The buried metal silicide layer can be formed by allotaxy or mesotaxy. The vertical semiconductor structure can be formed by epitaxially growing a semiconductor material on an etched surface of the doped portion of the semiconductor substrate.

Abstract: A dynamic random access memory element that includes a vertical semiconductor transistor element formed on a substrate and electrically connected with a memory element such as a capacitive memory element. The memory element is located above the semiconductor substrate such that the vertical transistor is between the memory element and the substrate. The vertical semiconductor transistor is formed on a heavily doped region of the substrate that is separated from other portions of the substrate by a dielectric isolation layer. The heavily doped region of the semiconductor substrate provides electrical connection between the vertical transistor structure and a bit line. The dynamic random access memory element also includes a word line that includes an electrically conductive gate layer that is separated from the semiconductor pillar by a gate dielectric layer.

Abstract: A vertical transistor structure having a metal gate wordline. The vertical transistor structure can include an epitaxially grown semiconductor column surrounded by a thin gate dielectric layer. A gate structure can surround the semiconductor column and the gate dielectric layer. The device can include first and second dielectric layers and an electrically conductive metal layer located between the first and second dielectric layers. The electrically conductive metal of the gate structure can be tungsten (W). In addition, a thin layer of Ti or TiN can be formed between the metal gate layer and the first and second dielectric layers and the gate dielectric layer. The metal gate layer can be formed with or without the use of a sacrificial layer.

Abstract: A DRAM memory cell and memory cell array incorporating a metal silicide bit line buried within a doped portion of a semiconductor substrate and a vertical semiconductor structure electrically connected with a memory element such as a capacitive memory element. The buried metal silicide layer functions as a bit buried bit line which can provide a bit line voltage to the capacitive memory element via the vertical transistor structure. The buried metal silicide layer can be formed by allotaxy or mesotaxy. The vertical semiconductor structure can be formed by epitaxially growing a semiconductor material on an etched surface of the doped portion of the semiconductor substrate.

Abstract: A dynamic random access memory element that includes a vertical semiconductor transistor element formed on a substrate and electrically connected with a memory element such as a capacitive memory element. The memory element is located above the semiconductor substrate such that the vertical transistor is between the memory element and the substrate. The vertical semiconductor transistor is formed on a heavily doped region of the substrate that is separated from other portions of the substrate by a dielectric isolation layer. The heavily doped region of the semiconductor substrate provides electrical connection between the vertical transistor structure and a bit line. The dynamic random access memory element also includes a word line that includes an electrically conductive gate layer that is separated from the semiconductor pillar by a gate dielectric layer.

Abstract: A magnetic memory structure that includes a two-terminal resistive memory element electrically connected with a selector structure. The selector structure includes a semiconductor pillar structure formed on a semiconductor substrate. The selector structure is surrounded by a gate dielectric layer, and the semiconductor pillar structure and gate dielectric layer are surrounded by an electrically conductive gate structure. The semiconductor pillar has first and second dimensions in a plane parallel with the surface of the semiconductor substrate that are unequal with one another. The semiconductor pillar structure can have a cross-section parallel with the semiconductor substrate surface that is in the shape of a: rectangle; oval elongated polygon, etc. The length of the longer dimension can be adjusted to provide a desired amount of current though the semiconductor pillar structure to drive the two-terminal resistive memory element.

Abstract: A memory array for data recording that includes a selector transistor electrically connected with a two terminal resistive memory element such as a magnetic tunnel junction (MTJ) element. The selector transistor comprises a semiconductor column formed by selective epitaxial growth on a semiconductor surface. The semiconductor column is at least partially surrounded by a gate dielectric layer and an electrically conductive gate structure arranged such that the gate dielectric is between the electrically conducive gate structure and the semiconductor column. The selective epitaxial growth of the semiconductor column allows the semiconductor column to have a very low electrical resistance in an “on” state which allows the selector transistor to provide a high electrical current to the two terminal resistive memory element for reliable switching during data writing.

Abstract: A processor-implemented method, according to one embodiment, includes: activating a subset of a plurality of p-MTJ cells oriented in one or more columns of a MRAM array. Activating the subset of p-MTJ cells includes: applying a first voltage to a gate terminal of the transistor in each of the p-MTJ cells in parallel, applying a second voltage to a first end of the MTJ sensor in each of the p-MTJ cells in parallel, and applying a third voltage to a drain terminal of the transistor in each of the p-MTJ cells in parallel. The processor-implemented method also includes: monitoring the activated subset of p-MTJ cells, determining whether any of the activated p-MTJ cells have failed, and in response to determining that an activated p-MTJ cell has failed, physically locating the failed p-MTJ cell. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: An interconnect assembly is for use in connection a semiconductor device under test (DUT) having a plurality of leads to electronic test equipment. The interconnect assembly includes a cable including a plurality of wires with a least one wire for sensing a signal from a DUT, at least one wire for a forcing signal to the DUT, and at least one wire for a guarding signal driven by the same electrical potential as the forcing signal. A male connector includes the plurality of wires, an outer metal coating surrounding the plurality of wires, and an insulating coating around the outer metal coating. A receptacle connector is for receiving the male connector and plurality of wires with corresponding contacts.

Abstract: A pulsed current generator circuit for providing current pulses to a device under test includes a current source for applying a current to the device under test and a controlled current shunt for shunting current from the device under test. A booster circuit is provided for supplying a booster current to the device under test when the controlled current shunt is opened and current again flows through the device under test, thereby facilitating recharge of a parasitic capacitance associated with the device under test.

Abstract: In an electrical for testing electrical current using a plurality of precision resistors connected in parallel or in series, a range finder for receiving the current to be measured with the voltage drop across the range finder being indicative of a current sub-range for measurement. In a preferred embodiment, a range finder comprises a first bipolar transistor and a second bipolar transistor connected in parallel and in opposite polarity with the emitter and base of each transistor connected together whereby each transistor functions as an emitter-base diode.

Abstract: A dual channel source measurement unit for reliability testing of electrical devices provides a voltage stress stimulus to a device under test and monitors degradation to the device under test caused by the stress simulator. The dual channel source measurement unit decouples the stress and monitor portions of the unit so that the requirements of each can be optimized. Deglitching and current clamp switches can be incorporated in the dual channel source measurement unit to prevent glitches in the switching circuitry and to limit or clamp current flow to or from the monitor and stress sources.

Abstract: A pulsed current generator circuit for providing current pulses to a device under test includes a current source for applying a current to the device under test and a controlled current shunt for shunting current from the device under test. A booster circuit is provided for supplying a booster current to the device under test when the controlled current shunt is opened and current again flows through the device under test, thereby facilitating recharge of a parasitic capacitance associated with the device under test.

Abstract: A test socket assembly for use in testing integrated circuits includes a spring holder plate having a plurality of holes for receiving a plurality of electrically conducting springs, and a plurality of electrically conducting springs in the plurality of holes. A test socket including a plurality of pins for receiving leads of an integrated circuit is mounted on the spring holder plate with the pins extending into the plurality of holes in the spring holder plate with each pin engaging a spring. The holder plate is positionable on a printed circuit board with the plurality of holes in the spring holder plate being in alignment with electrical contacts or pads on the printed circuit board, the plurality of springs electrically interconnecting the contacts and the plurality of pins.

Abstract: A test socket assembly for use in testing integrated circuits includes a spring holder plate having a plurality of holes for receiving a plurality of electrically conducting springs, and a plurality of electrically conducting springs in the plurality of holes. A test socket including a plurality of pins for receiving leads of an integrated circuit is mounted on the spring holder plate with the pins extending into the plurality of holes in the spring holder plate with each pin engaging a spring. The holder plate is positionable on a printed circuit board with the plurality of holes in the spring holder plate being in alignment with electrical contacts or pads on the printed circuit board, the plurality of springs electrically interconnecting the contacts and the plurality of pins.

Abstract: A minimal insertion force socket for use in testing DIP integrated circuits having a plurality of leads extending therefrom, the socket plate having a plurality of holes arranged in two parallel rows for receiving the leads from the integrated circuit, and a plurality of wires anchored on the socket plate and arranged in two parallel partially interdigitated sets with each wire cooperating with a hole for engaging a lead of the integrated circuit. The working distance from a lead contact point on each wire to an anchor point on the interdigitated portion of each wire is increased relative to the working distance of aligned wires in the two parallel sets.