Abstract: A socket for use in testing packaged integrated circuits having leads depending therefrom includes a first member for receiving the integrated package and having a plurality of first holes for receiving leads extending from the package. A second member has a plurality of wires for engaging the leads, each wire being anchored at ends to the second member with an intermediate portion engaging a lead. Each intermediate portion is aligned with a first hole and capable of being flexed out of alignment with the first hole for insertion of an integrated circuit package into the socket. The first member includes a second plurality of holes aligned with the wires of the second member, and an actuator has a plurality of pins arranged to extend into the second plurality of holes for engaging the plurality of wires and flexing the intermediate portions of the wires out of alignment with the first plurality of holes.

Abstract: A minimal insertion force socket for use in testing DIP integrated circuits having a plurality of leads extending therefrom, the socket plate having a plurality of holes arranged in two parallel rows for receiving the leads from the integrated circuit, and a plurality of wires anchored on the socket plate and arranged in two parallel partially interdigitated sets with each wire cooperating with a hole for engaging a lead of the integrated circuit. The working distance from a lead contact point on each wire to an anchor point on the interdigitated portion of each wire is increased relative to the working distance of aligned wires in the two parallel sets.

Abstract: A socket for use in testing packaged integrated circuits having leads depending therefrom includes a first member for receiving the integrated package and having a plurality of first holes for receiving leads extending from the package. A second member has a plurality of wires for engaging the leads, each wire being anchored at ends to the second member with an intermediate portion engaging a lead. Each intermediate portion is aligned with a first hole and capable of being flexed out of alignment with the first hole for insertion of an integrated circuit package into the socket. The first member includes a second plurality of holes aligned with the wires of the second member, and an actuator has a plurality of pins arranged to extend into the second plurality of holes for engaging the plurality of wires and flexing the intermediate portions of the wires out of alignment with the first plurality of holes.

Abstract: A socket for use in testing packaged integrated circuits having leads depending therefrom includes a first member for receiving the integrated circuit package and having a plurality of holes for receiving leads extending from the package. A second member has a plurality of wire contacts for engaging the leads, the first and second members being arranged to permit relative lateral translation thereof. A cam is provided for sliding the first member relative to the second member and moving leads extending through the holes in the first member into engagement with the contacts of the second member. A socket for dual in-line integrated circuit package (DIP) has two rows of holes in the first member, and two slots are provided in the second member each aligned with a row of holes. The wire contacts extend across each slot. For high temperature operation (greater than 250° C.) the first and second members comprise anodized aluminum or a ceramic, and the wires comprise Monel or other high temperature material.

Abstract: In the present invention, a voltage level shifting circuit is disclosed. The voltage level shifting circuit comprises a first inventer and a second inverter with each inverter having a P-type MOS transistor and an N-type MOS transistor. Each of the inverters has an input port, an output port, a first voltage port and a second voltage port. The source of the P-type MOS transistor or N-type MOS transistor of each inverter is connected to the first voltage port. The voltage level shifting circuit also comprises two MOS transistors of the same conductivity type as the transistors of the inverter whose source is connected to the first voltage port. Each of the MOS transistors has a source, a drain and a gate with the drain connected to the first voltage port of each of the inverters. The sources of the first and second MOS transistors are connected together and to a high voltage level, such as V.sub.pp.