Abstract: A memory system comprising an expansion buffer and a memory expansion channel for connecting a large array of memory devices, such as Direct RDRAMs, to a memory controller. The memory devices are partitioned into subsets of memory devices so that each subset is connected to a unique memory channel for sending and receiving data. The expansion buffer and memory expansion channel provide communication with the memory devices via control packets on the expansion bus, where each control packet has a channel identification field to store a channel identifier; and via request packets on the expansion bus, where each request packet is associated with a control packet. The expansion buffer routes a request packet to a unique channel based upon the channel identifier stored in the associated control packet.

Abstract: A method and apparatus for transferring data between bus agents in a computer system. The present invention includes transmitting a control signal, from a first agent to a second agent, via a first transfer protocol; and, transmitting data corresponding to the control signal, from the first agent to the second agent, via a second transfer protocol. In one embodiment, the control signals are transmitted from the first agent to the second agent via a synchronous transmission with respect to a bus clock; and, the data is transmitted via an asynchronous transmission with respect to the bus clock, which has a data width greater than the synchronous transmission. In addition, in one embodiment of the present invention, the synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.

Abstract: A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.

Abstract: A method and apparatus for detecting errors in data output from memory and a device failure in the memory. In the invention, a check code is generated based on data to be input to the memory. The check code is valid when equal to zero. The check code is inverted and input along with the data as a codeword to the memory in response to a write command. The codeword is output from the memory in response to a read command. The codeword output from memory indicates whether a device in memory has failed. The inverted check code included in the codeword output from memory is re-inverted. Information indicating whether the data included in the codeword output from memory includes an error is generated based on the data and the codeword including the check code.

Abstract: A method and apparatus for supporting multiple overlapping address spaces on a shared bus includes both an address comparator and an address size indicator. The address comparator compares an address, corresponding to a request to be issued on the bus, to a plurality of address spaces. The address size indicator indicates a first address space of the plurality of address spaces to which the address corresponds.

Abstract: A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus. A method includes determining whether a memory device to which signals are addressed is on a first memory module. Signals are routed to a first memory bus on the first memory module connected to the memory device if the memory is on the first memory module. Signals are routed to a second memory bus on a second memory module if the memory device is not on the first memory module.

Abstract: A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.

Abstract: A method and apparatus for supporting multiple overlapping address spaces on a shared bus includes both an address comparator and an address size indicator. The address comparator compares an address, corresponding to a request to be issued on the bus, to a plurality of address spaces. The address size indicator indicates a first address space of the plurality of address spaces to which the address corresponds.

Abstract: A data flow control mechanism for a bus supporting two- and three-agent transactions includes a control logic to place an indication of a request onto a computer system bus. The agent placing the indication on the bus then waits to place data corresponding to the request onto the bus until it has received an indication from another agent coupled to the bus that the other agent is ready to receive the data.

Abstract: A method and apparatus for transferring data between bus agents in a computer system. The present invention includes transmitting a control signal, from a first agent to a second agent, via a first transfer protocol; and, transmitting data corresponding to the control signal, from the first agent to the second agent, via a second transfer protocol. In one embodiment, the control signals are transmitted from the first agent to the second agent via a synchronous transmission with respect to a bus clock; and, the data is transmitted via an asynchronous transmission with respect to the bus clock, which has a data width greater than the synchronous transmission. In addition, in one embodiment of the present invention, the synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.

Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.

Abstract: A memory module includes a first memory bus. A memory repeater hub is coupled to the first memory bus. A second memory bus is coupled in series with the memory repeater hub.

Abstract: A method and apparatus for transferring data between bus agents in a computer system. The present invention includes transmitting a control signal, from a first agent to a second agent, via a first transfer protocol; and, transmitting data corresponding to the control signal, from the first agent to the second agent, via a second transfer protocol. In one embodiment, the control signals are transmitted from the first agent to the second agent via a synchronous transmission with respect to a bus clock; and, the data is transmitted via an asynchronous transmission with respect to the bus clock, which has a data width greater than the synchronous transmission. In addition, in one embodiment of the present invention, the synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.

Abstract: A method and apparatus for supporting multiple overlapping address spaces on a shared bus includes both an address comparator and an address size indicator. The address comparator compares an address, corresponding to a request to be issued on the bus, to a plurality of address spaces. The address size indicator indicates a first address space of the plurality of address spaces to which the address corresponds.

Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.

Abstract: A method and apparatus for supporting multiple overlapping address spaces on a shared bus includes both an address comparator and an address size indicator. The address comparator compares an address, corresponding to a request to be issued on the bus, to a plurality of address spaces. The address size indicator indicates a first address space of the plurality of address spaces to which the address corresponds.

Abstract: A method and apparatus for communicating signals between a source synchronous component and a non-source synchronous component of a system is described. The present invention provides a strobe signal from the source synchronous component that is delayed and used to latch data received from a non-source synchronous component. The amount of delay provided is determined based on the timing of data request cycles to the non-source synchronous component. Thus, the present invention allows data to be received by a source synchronous component from a component that does not generate a strobe signal used for latching received data that would be generated by a source synchronous component.

Abstract: A digital system includes a clock line carrying a clock signal and a communication bus with a signal time of flight longer than a cycle of the clock signal. A master device is connected to the communication bus and the clock line. The master device selectively applies signals to the communication bus. A set of slave devices are connected to the communication bus and the clock line. Each slave device of the set of slave devices has an associated latency delay arising from its position on the communication bus. Each slave device includes delay circuitry to compensate for the associated latency delay such that the master device observes a uniform minimum latency for each slave device in response to applying signals to the communication bus.

Abstract: A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

Abstract: A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This visibility indication allows the bus agent to proceed with the next ordered transaction without waiting for the completion status of the deferred transaction. The visibility indication provides fast processing of ordered transactions.