Patents by Inventor Peter D. MacWilliams

Peter D. MacWilliams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5625779
    Abstract: An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for storing data to be written into the DRAM. The host bridge also includes an arbiter coupled to receive a request signal from the expansion bridge and any other bus agents coupled to the expansion bridge. Responsive to a request from the expansion bridge, the arbiter empties the CPU posting buffer and the DRAM buffer before asserting an acknowledge signal. A passive release method is provided, which includes signaling a passive release semantic by the expansion bridge during a communication cycle in which the expansion bridge has bus control. The host bridge can grant temporary use of the bus to another bus agent before again granting access to the expansion bridge.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: April 29, 1997
    Assignee: Intel Corporation
    Inventors: Gary A. Solomon, Peter D. MacWilliams, George R. Hayek, Nicholas D. Wade, Abid Asghar
  • Patent number: 5615343
    Abstract: A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: March 25, 1997
    Assignee: Intel Corporation
    Inventors: Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh, Peter D. MacWilliams, Stephen S. Pawlowski, Michael W. Rhodehamel
  • Patent number: 5555423
    Abstract: In a high performance multi-mode microprocessor, apparatus and a method for switching between modes while selectively maintaining the contents of selected memory elements inside the microprocessor, including a cache and floating point registers. The microprocessor described herein includes an electrical pin provided externally on the microprocessor chip package, that is connected to a control unit, which is connected to a plurality of registers. Microcode is provided, accessible to the microprocessor, that re-initializes some, but not all, of the microprocessor's registers and caches to their initial state, so that the microprocessor is placed in its initial mode of operation. In operation, the pin is actuated by an electrical signal provided from any of a number of conventional sources, such as an I/O port. Actuation of the pin in turn actuates the control unit, to assert a high priority interrupt.
    Type: Grant
    Filed: July 26, 1995
    Date of Patent: September 10, 1996
    Assignee: Intel Corporation
    Inventors: Edward T. Grochowski, Peter D. MacWilliams
  • Patent number: 5537640
    Abstract: An asynchronous computer bus and method to maintain consistency of data contained in a cache and a memory which are each coupled to the bus. The bus comprises a cache hit indication means, a write access indication means, and a modified data indication means. A means is provided for invalidating a first portion of the cache, the invalidation means being operative upon activation of the cache hit indication means. Further, the bus comprises a modified data indication means and the write access indication means. A write-back means is provided for writing back the first portion of the cache data to the memory, the write back means being operative upon the first portion of the cache being invalidated by the invalidation means. Lastly, the bus comprises a shared data indication means which is operative on the cache hit indication means and upon failure of activation of the write access determination means.
    Type: Grant
    Filed: June 10, 1994
    Date of Patent: July 16, 1996
    Assignee: Intel Corporation
    Inventors: Stephen S. Pawlowski, Peter D. MacWilliams, David M. Cowan, Howard S. David
  • Patent number: 5513331
    Abstract: An apparatus and method for assigning memory address information in a computer system. The present invention relates to computer systems having a plurality of ports or slots for coupling boards or other apparatus accessible to a processor of the computer system. The computer system further comprises an address decoder electrically coupled with the ports and processor. The address decoder receives, preferably at the time the computer system is first powered on, memory size identifying information from each of the memory boards coupled with the plurality of slots. The address decoder assigns system address space to each of the individual memories.
    Type: Grant
    Filed: March 29, 1995
    Date of Patent: April 30, 1996
    Assignee: Intel Corporation
    Inventors: Stephen Pawlowski, Peter D. MacWilliams
  • Patent number: 5488639
    Abstract: A method and apparatus for synchronizing an asynchronous signal to a clock signal. The apparatus includes an enable generator, first, second and third sampling circuits, a selecting circuit, and can include a latching circuit. The enable generator is coupled to the first sampling circuit by a first enable line, to the second sampling circuit by a second enable line, and to the third sampling circuit by a third enable line. The first, second, and third sampling circuits are coupled to receive the asynchronous signal. The selecting circuit is coupled to receive the output signals of the first, second and third sampling circuits. For the first sampling circuit, the following steps are performed: sampling the asynchronous signal, generating an output signal for the sampling circuit, waiting a period of time, and selecting the sampling circuit's output signal. These steps are also performed for the second sampling circuit and the third sampling circuit.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: January 30, 1996
    Assignee: Intel Corporation
    Inventors: Peter D. MacWilliams, Dror Avni, Avi Liebermensch, Anan Baransy, Robert L. Farrell
  • Patent number: 5471637
    Abstract: An asynchronous computer bus providing transfers of data on consecutive processor clock cycles. The bus comprises consecutive data transfer commence indication means, starting address transmission means, consecutive data transfer indication means, and data transmission means. The invention provides for the "burst" capabilities of modern processors wherein entire blocks of data are transmitted within a single request.
    Type: Grant
    Filed: April 26, 1995
    Date of Patent: November 28, 1995
    Assignee: Intel Corporation
    Inventors: Stephen S. Pawlowski, Peter D. MacWilliams, Jerzy B. Kolinski
  • Patent number: 5455957
    Abstract: An apparatus and method for communicating characteristics about a memory module to a processor unit. A method and apparatus for communicating memory module characteristics, such as whether the module can communicate in a deterministic mode, memory size, memory speed, memory type and whether the memory is cachable to a processor. In the present invention, the processor asserts a request signal onto the system bus and the memory module corresponding to the address of the request respond with information regarding its characteristics.
    Type: Grant
    Filed: February 27, 1995
    Date of Patent: October 3, 1995
    Assignee: Intel Corporation
    Inventors: Stephen Pawlowski, Peter D. MacWilliams
  • Patent number: 5355467
    Abstract: A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.
    Type: Grant
    Filed: March 8, 1994
    Date of Patent: October 11, 1994
    Assignee: Intel Corporation
    Inventors: Peter D. MacWilliams, Robert L. Farrell, Adalberto Golbert, Itzik Silas
  • Patent number: 5301299
    Abstract: An improved method for accessing memory in a computer system using standard fast paged mode memory access for a second memory access where the second memory access is pending at the completion of a first memory access. However, if at the completion of a first memory access there is no pending memory request, the RAS line of the memory is deactivated allowing precharge during an idle state on the bus.
    Type: Grant
    Filed: February 16, 1993
    Date of Patent: April 5, 1994
    Assignee: Intel Corporation
    Inventors: Stephen Pawlowski, Peter D. MacWilliams
  • Patent number: 5293603
    Abstract: An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus interface and a main memory bus interface. The CPU bus and main memory bus interfaces include multiplexers, buffers, and local control for optimizing burst read and write operations to and from the CPU bus. These circuits allow a full cache line to be read or written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.
    Type: Grant
    Filed: June 4, 1991
    Date of Patent: March 8, 1994
    Assignee: Intel Corporation
    Inventors: Peter D. MacWilliams, Clair C. Webb, Robert L. Farrell
  • Patent number: 5239638
    Abstract: An apparatus and method for allowing improved access to a memory by a processor utilizing a two strobed memory access protocol. The present invention discloses a method and apparatus for allowing a processor to request access to a memory over a communication bus, the processor retains control of the bus, and access to the memory, during the period of time it asserts an access strobe signal. The memory will respond to write or read requests to the memory during this period of time and the processor may address memory locations in a given page of the memory during this period of time. These accesses which occur during this period of time are initiated or terminated by a second access strobe signal while the first strobe remains active. This allows for more improved memory access times by holding it active during this multiple access window.
    Type: Grant
    Filed: September 5, 1989
    Date of Patent: August 24, 1993
    Assignee: Intel Corporation
    Inventors: Stephen Pawlowski, Peter D. MacWilliams
  • Patent number: 5228134
    Abstract: An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface incorporating multiplexers and buffers circuits for optimizing burst read and write operations across the CPU bus. Theses circuits allow a full cache line to be read/written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.
    Type: Grant
    Filed: June 4, 1991
    Date of Patent: July 13, 1993
    Assignee: Intel Corporation
    Inventors: Peter D. MacWilliams, Clair C. Webb, Robert L. Farrell
  • Patent number: 4785396
    Abstract: A high speed serial bus is disclosed have particular application for use in passing messages in a multiple processor computer system. The serial bus includes a three-wire serial link having lines identified as "SDA", "SDB" and "ground". The ground line provides a common reference for all devices coupled to the serial bus. A message controller is coupled to each agent for transmitting and receiving serial data along the bus. Both lines of the serial bus as well as the ground are coupled to a bus state detector in the message controller which provides three basic signal outputs. The bus state detector determines whether or not the bus is in use, a collision has occurred between messages, and decodes data received on the bus. Data which is transmitted along the serial bus is driven on lines SDA and SDB 180 degrees out of phase relative to each other. The message controller encodes messages to be transmitted using, in the present embodiment, well known Manchester encoding techniques.
    Type: Grant
    Filed: January 26, 1988
    Date of Patent: November 15, 1988
    Assignee: Intel Corporation
    Inventors: Sean T. Murphy, Narjala Bhasker, Peter D. MacWilliams, Stephen J. Packer