Abstract: A method for removal of post reactive ion etch by-product from a semiconductor wafer surface or microelectronic composite structure comprising: supplying a reducing gas plasma incorporating a forming gas mixture selected from the group consisting of a mixture of N2/H2 or a mixture of NH3/H2 into a vacuum chamber in which a semiconductor wafer surface or a microelectronic composite structure is supported to form a post-RIE polymer material by-product on the composite structure without significant removal of an organic, low K material which has also been exposed to the reducing gas plasma; and removing the post-RIE polymer material by-product with a wet clean.

Abstract: An apparatus and method for controlling wafer temperature and environment is provided. The apparatus includes a batch processing fixture for batch processing wafers at a first elevated temperature. The batch of wafers is not substantially ramped in temperature within the batch processing fixture. The apparatus also includes a single wafer processing apparatus for rapidly ramping temperature of a wafer of the batch from the first elevated temperature wherein a uniform temperature across the wafer is maintained during the ramping. Another embodiment of the apparatus (10) includes an RTP chamber (20) having an inert or reducing environment and that includes a pedestal (24) for holding a single wafer (16) and a heater unit (22) arranged so as to uniformly and rapidly heat the single wafer.

Abstract: A method for removal of post reactive ion etch by-product from a semiconductor wafer surface or microelectronic composite structure comprising:

Abstract: An on-chip vertically stacked decoupling capacitor includes a hardmask film formed between the capacitor dielectric and the lower electrode. The manufacturing process used to form the capacitor takes advantage of the hardmask film and enables the capacitor to be formed over a low-k dielectric material. Attack of the underlying low-k dielectric material is suppressed during the etching and stripping processes used to form the capacitor, due to the presence of the hardmask. The low-k dielectric film provides for a reduced parasitic capacitance between adjacent conductive wires formed in the low-k dielectric material and therefore provides for increased levels of integration.

Abstract: An on-chip vertically stacked decoupling capacitor includes a hardmask film formed between the capacitor dielectric and the lower electrode. The manufacturing process used to form the capacitor takes advantage of the hardmask film and enables the capacitor to be formed over a low-k dielectric material. Attack of the underlying low-k dielectric material is suppressed during the etching and stripping processes used to form the capacitor, due to the presence of the hardmask. The low-k dielectric film provides for a reduced parasitic capacitance between adjacent conductive wires formed in the low-k dielectric material and therefore provides for increased levels of integration.

Abstract: An on-chip vertically stacked decoupling capacitor includes a hardmask film formed between the capacitor dielectric and the lower electrode. The manufacturing process used to form the capacitor takes advantage of the hardmask film and enables the capacitor to be formed over a low-k dielectric material. Attack of the underlying low-k dielectric material is suppressed during the etching and stripping processes used to form the capacitor, due to the presence of the hardmask. The low-k dielectric film provides for a reduced parasitic capacitance between adjacent conductive wires formed in the low-k dielectric material and therefore provides for increased levels of integration.

Abstract: A vertical channel field effect transistor and a process of manufacturing the same. The vertical channel field effect transistor is disposed on a surface of a substrate and comprises an epitaxial silicon stack having a bottom terminal comprising heavily doped silicon, a channel comprising lightly doped silicon of opposite doping type from the bottom terminal, and a top terminal comprising heavily doped silicon of the same doping type as the bottom terminal. The vertical channel field effect transistor also comprises a gate dielectric layer covering at least a portion of the bottom terminal, the channel, and the top terminal, and a gate in contact with the gate dielectric layer. The gate is positioned adjacent the channel and adjacent at least a portion of the bottom terminal and top terminal. The channel has a thickness between the bottom terminal and the top terminal from about 50 angstroms to about 800 angstroms.

Abstract: A pass-through, wafer-processing tool for treating a moving semiconductor wafer with a process gas. The tool comprises an open-ended, non-isolated processing module having a wafer path through the module, vacuum manifolds mounted adjacent the wafer entry to and wafer exit from the module, and a gas manifold between the vacuum manifolds adapted to direct process gas onto the moving wafer. The gas manifold may deliver plasma ions generated by a remote plasma unit outside the module. Instead, a plasma may be generated inside the pass-through, wafer processing tool and, if so, the tool further comprises a top electrode mounted above the wafer passage. A wafer handler, which may be a robotic handler, carries the wafer through the wafer passage and serves as a bottom electrode.