Patents by Inventor Peter Feeley
Peter Feeley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966616Abstract: A current value for a reference voltage for a block family is determined. An amount of voltage shift for a memory page of the block family is determined based on the current value for the reference voltage and a prior value for the reference voltage. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.Type: GrantFiled: February 27, 2023Date of Patent: April 23, 2024Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Mustafa N. Kaynak, Peter Feeley, Sivagnanam Parthasarathy, Sampath Ratnam, Shane Nowell
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Publication number: 20240126690Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
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Publication number: 20240111445Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Michael Sheperek, Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz
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Publication number: 20240103749Abstract: At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Inventors: Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
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Patent number: 11928347Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; identify, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block; identify, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.Type: GrantFiled: February 27, 2023Date of Patent: March 12, 2024Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Mustafa N Kaynak, Peter Feeley, Sampath K Ratnam, Shane Nowell, Sivagnanam Parthasarathy, Karl D Schuh, Jiangang Wu
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Patent number: 11899966Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.Type: GrantFiled: July 25, 2022Date of Patent: February 13, 2024Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Mark A. Helm, Giuseppina Puzzilli, Peter Feeley, Yifen Liu, Violante Moschiano, Akira Goda, Sampath K. Ratnam
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Publication number: 20240045616Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.Type: ApplicationFiled: August 5, 2022Publication date: February 8, 2024Inventors: Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Dave Scott Ebsen, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Jiangli Zhu, Fangfang Zhu, Akira Goda
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Patent number: 11886726Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.Type: GrantFiled: December 6, 2021Date of Patent: January 30, 2024Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz
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Publication number: 20240028259Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.Type: ApplicationFiled: July 21, 2022Publication date: January 25, 2024Inventors: Kishore Kumar Muchherla, Peter Feeley, Jiangli Zhu, Fangfang Zhu, Akira Goda, Lakshmi Kalpana Vakati, Vivek Shivhare, Dave Scott Ebsen, Sanjay Subbarao
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Publication number: 20240029815Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.Type: ApplicationFiled: July 25, 2022Publication date: January 25, 2024Inventors: Kishore Kumar Muchherla, Akira Goda, Dave Scott Ebsen, Lakshmi Kalpana Vakati, Jiangli Zhu, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Fangfang Zhu
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Patent number: 11869605Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing a read operation on a block of the memory device by applying a read reference voltage to a selected wordline of the block and applying a pass-through voltage having a first value to a plurality of unselected wordlines of the block; detecting a read error in response to performing the read operation; and setting the pass-through voltage to a second value, wherein the second value is greater than the first value.Type: GrantFiled: August 17, 2022Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Sampath K Ratnam, Peter Feeley, Sivagnanam Parthasarathy
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Patent number: 11868639Abstract: At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.Type: GrantFiled: June 17, 2021Date of Patent: January 9, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
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Patent number: 11853207Abstract: The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring a set of trim settings for an array of memory cells such that the array of memory cells have desired operational characteristics in response to being operated with the set of trim settings.Type: GrantFiled: June 2, 2021Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
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Patent number: 11854634Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.Type: GrantFiled: August 31, 2020Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L Lowrance, Peter Feeley
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Patent number: 11853205Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.Type: GrantFiled: February 21, 2023Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
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Patent number: 11836392Abstract: A processing device in a memory sub-system identifies a plurality of word lines at a first portion of a memory device, determines a respective error rate for each of the plurality of word lines, and determines that a first error rate of a first word line of the plurality of word lines and a second error rate of a second word line of the plurality of word lines satisfy a first threshold condition pertaining to an error rate threshold. The processing device further identifies a third word line of the plurality of word lines that is proximate to the first word line and the second word line and relocates data stored at the third word line to a second portion of the memory device, wherein the second portion of the memory device is associated with a lower read latency than the first portion of the memory device.Type: GrantFiled: October 12, 2021Date of Patent: December 5, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Harish R. Singidi, Peter Feeley
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Patent number: 11837307Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing, on data residing in a block of the memory device, an error-handling operation of a plurality of error-handling operations, wherein an order of the plurality of error-handling operations is based on a voltage offset bin associated with the block, wherein the voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations; and responsive to determining that the error-handling operation has failed to recover the data, adjusting the order of the plurality of error-handling operations.Type: GrantFiled: November 2, 2022Date of Patent: December 5, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy, Devin M. Batutis, Xiangang Luo
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Patent number: 11836078Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.Type: GrantFiled: January 14, 2022Date of Patent: December 5, 2023Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Daniel L Lowrance, Peter Feeley
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Patent number: 11823722Abstract: A processing device of a memory sub-system is configured to identify a read level of a plurality of read levels associated with a voltage bin of a plurality of voltage bins of a memory device; assign a first threshold voltage offset to the read level of the voltage bin; assign a second threshold voltage offset to the read level of the voltage bin; perform, on block associated with the read level, a first operation of a first operation type using the first threshold voltage offset; and perform, on the blocks associated with the read level, a second operation of a second operation type using the second threshold voltage offset.Type: GrantFiled: February 15, 2023Date of Patent: November 21, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Mustafa N Kaynak, Sampath K Ratnam, Shane Nowell, Peter Feeley, Sivagnanam Parthasarathy
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Patent number: 11823748Abstract: A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.Type: GrantFiled: August 18, 2022Date of Patent: November 21, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Karl Schuh, Mustafa N Kaynak, Xiangang Luo, Shane Nowell, Devin Batutis, Sivagnanam Parthasarathy, Sampath Ratnam, Jiangang Wu, Peter Feeley