Patents by Inventor Peter Feeley

Peter Feeley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230017591
    Abstract: An initial value of a power cycle count associated with the memory device is identified. The power cycle count is incremented responsive to detecting a powering up of the memory device. Responsive to programming a block residing in the memory device, the block is associated with a current block family associated with the memory device. A currently value of the power cycle count is determined. Responsive to determining that a difference between the initial value of the power cycle count and the current value of the power cycle count satisfies a predefined condition, the current block family is closed.
    Type: Application
    Filed: September 21, 2022
    Publication date: January 19, 2023
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Peter Feeley, Karl D. Schuh
  • Patent number: 11544188
    Abstract: Memory circuits including dynamically configurable cache cells are disclosed herein. The cache cells may be selectively and dynamically configured to select one or more bits per cell according to a real-time determination or characterization of a workload type.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: January 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yun Li, Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam
  • Publication number: 20220414021
    Abstract: A first block that is assigned a first sequence identifier can be identified. A determination can be made as to whether the assigned first sequence identifier satisfies a threshold sequence identifier condition that corresponds to a difference between the first sequence identifier assigned to the first block and second sequence identifier assigned to a second block. In response to determining that the assigned first sequence identifier satisfies the threshold sequence identifier condition, a media management operation can be performed on the first block.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 29, 2022
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Ashutosh Malshe
  • Patent number: 11532373
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an order of a plurality of error-handling operations to be performed to recovery data associated with the read error, wherein the order is specified in a metadata table and is based on the voltage offset bin associated with the block, and performing at least one error-handling operation of the plurality of error-handling operations in the order specified by the metadata table.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: December 20, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy, Devin M. Batutis, Xiangang Luo
  • Publication number: 20220392554
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing a read operation on a block of the memory device by applying a read reference voltage to a selected wordline of the block and applying a pass-through voltage having a first value to a plurality of unselected wordlines of the block; detecting a read error in response to performing the read operation; and setting the pass-through voltage to a second value, wherein the second value is greater than the first value.
    Type: Application
    Filed: August 17, 2022
    Publication date: December 8, 2022
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy
  • Publication number: 20220392547
    Abstract: A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.
    Type: Application
    Filed: August 18, 2022
    Publication date: December 8, 2022
    Inventors: Kishore Kumar Muchherla, Karl Schuh, Mustafa N. Kaynak, Xiangang Luo, Shane Nowell, Devin Batutis, Sivagnanam Parthasarathy, Sampath Ratnam, Jiangang Wu, Peter Feeley
  • Patent number: 11520699
    Abstract: A processing device of a memory sub-system is configured to receive a request to add content to a system data structure, wherein a first plurality of blocks of a common pool of blocks are allocated to the system data structure and a second plurality of blocks of the common pool of blocks are allocated to user data; determine whether user data has been written to the second plurality of blocks of the common pool of blocks within a threshold amount of time; and responsive to determining that the user data has not been written to the second plurality of blocks within the threshold amount of time, allocate a block from the second plurality of blocks of the common pool of blocks allocated to user data to the first plurality of blocks of the common pool of blocks allocated for the system data structure.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: December 6, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Kulachet Tanpairoj, Peter Feeley, Sampath K. Ratnam, Ashutosh Malshe
  • Publication number: 20220383955
    Abstract: A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Inventors: Kishore Kumar MUCHHERLA, Sampath K. RATNAM, Shane NOWELL, Sivagnanam PARTHASARATHY, Mustafa N. KAYNAK, Karl D. SCHUH, Peter FEELEY, Jiangang WU
  • Patent number: 11500564
    Abstract: A block family associated with a memory device is initialized. An initial value of a power cycle count associated with the memory device is stored. Responsive to programming a block residing in the memory device, the block is associated with the block family. Responsive to determining that a current value of the power cycle count exceeds the initial value of the power cycle count, the block family is closed. Responsive to determining that a time period that has elapsed since initializing the block family exceeds a threshold period, the block family is closed.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: November 15, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Peter Feeley, Karl D. Schuh
  • Publication number: 20220357873
    Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Kishore Kumar Muchherla, Mark A. Helm, Giuseppina Puzzilli, Peter Feeley, Yifen Liu, Violante Moschiano, Akira Goda, Sampath K. Ratnam
  • Publication number: 20220351786
    Abstract: A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
    Type: Application
    Filed: July 19, 2022
    Publication date: November 3, 2022
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy, Qisong Lin, Shane Nowell, Mustafa N. Kaynak
  • Publication number: 20220336023
    Abstract: A processing device of a memory sub-system is configured to identify a read level of a plurality of read levels associated with a voltage bin of a plurality of voltage bins of a memory device; assign a first threshold voltage offset to the read level of the voltage bin; assign a second threshold voltage offset to the read level of the voltage bin; perform, on block associated with the read level, a first operation of a first operation type using the first threshold voltage offset; and perform, on the blocks associated with the read level, a second operation of a second operation type using the second threshold voltage offset.
    Type: Application
    Filed: April 16, 2021
    Publication date: October 20, 2022
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Sampath K. Ratnam, Shane Nowell, Peter Feeley, Sivagnanam Parthasarathy
  • Publication number: 20220334721
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to perform operations comprising assigning a plurality of data streams to a block family comprising a plurality of blocks of a memory device; responsive to programming a first block associated with a first data stream of the plurality of data streams, associating the first block with the block family; and responsive to programming a second block associated with a second data stream of the plurality of data streams, associating the second block with the block family.
    Type: Application
    Filed: June 22, 2022
    Publication date: October 20, 2022
    Inventors: Michael Sheperek, Bruce A. Liikanen, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz
  • Publication number: 20220334752
    Abstract: A processing device of a memory sub-system is configured to identify a plurality of blocks assigned to a first voltage bin of a plurality of voltage bins of a memory device; identify a subset of the plurality of blocks having a time after program (TAP) within a predetermined threshold period of time from a second TAP associated with a transition boundary between the first voltage bin and a subsequent voltage bin of the plurality of voltage bins; determine a threshold voltage offset associated with the subset of blocks; and associate the threshold voltage offset with the subsequent voltage bin.
    Type: Application
    Filed: April 16, 2021
    Publication date: October 20, 2022
    Inventors: Kishore Kumar MUCHHERLA, Sampath K RATNAM, Shane NOWELL, Peter FEELEY, Sivagnanam Parthasarathy, Mustafa N Kaynak
  • Patent number: 11467980
    Abstract: A first block that is assigned a first sequence identifier can be identified. A determination can be made as to whether the assigned first sequence identifier satisfies a threshold sequence identifier condition that corresponds to a difference between the first sequence identifier assigned to the first block and second sequence identifier assigned to a second block. In response to determining that the assigned first sequence identifier satisfies the threshold sequence identifier condition, a media management operation can be performed on the first block.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: October 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Ashutosh Malshe
  • Publication number: 20220317902
    Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; divide the sorted plurality of blocks into a plurality of block segments; scan a first block at a first boundary of a first block segment of the plurality of block segments; scan a second block at a second boundary of the first block segment; identify, based on a scanning result of the first block, a first voltage bin associated with the first block; identify, based on a second scanning result of the second block, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block of a subset of the plurality of blocks assigned to the first block segment.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Peter Feeley, Sampath K. Ratnam, Shane Nowell, Sivagnanam Parthasarathy, Karl D. Schuh, Jiangang Wu
  • Publication number: 20220318086
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an ordered set of error-handling operations to be performed to the data, determining a most recently performed error-handling operation associated with the voltage offset bin; adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 6, 2022
    Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy, Devin M. Batutis, Xiangang Luo
  • Patent number: 11462280
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including receiving a read command to perform a read operation on a block of the memory device, determining a pass-through voltage for the block based on a metadata table, and performing the read operation by applying a read reference voltage to a selected wordline of the block and applying the pass-through voltage to a plurality of unselected wordlines of the block.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: October 4, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy
  • Publication number: 20220300415
    Abstract: A total estimated occupancy value of a first data on a first data block of a plurality of data blocks is determined. To determine the total estimated occupancy value of the first data block, a total block power-on-time (POT) value of the first data block is determined. Then, a scaling factor is applied to the total block POT value to determine the total estimated occupancy value of the first data block. Whether the total estimated occupancy value of the first data block satisfies a threshold criterion is determined. Responsive to determining that the total estimated occupancy value of the first data block satisfies the threshold criterion, data stored at the first data block is relocated to a second data block of the plurality of data blocks.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Inventors: Kishore Kumar MUCHHERLA, Renato C. PADILLA, Sampath K. RATNAM, Saeed SHARIFI TEHRANI, Peter FEELEY, Kevin R. BRANDT
  • Publication number: 20220300186
    Abstract: A current memory access voltage distribution is measured for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device. The first voltage bin is associated with a first voltage offset. A current value for a reference voltage is determined based on the current memory access voltage distribution measured for the memory page. An amount of voltage shift for the memory page is determined based on the current value for the reference voltage a prior value for the reference voltage. The prior value for the reference voltage is associated with a prior memory access voltage distribution for the memory page. In response to a determination that the amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the plurality of voltage bins. The second voltage bin is associated with a second voltage offset.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 22, 2022
    Inventors: Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Mustafa N. Kaynak, Peter Feeley, Sivagnanam Parthasarathy, Sampath Ratnam, Shane Nowell