Patents by Inventor Peter Feeley

Peter Feeley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SELECTIVE ACCELERATED SAMPLING OF FAILURE-SENSITIVE MEMORY PAGES
    Publication number: 20220229564
    Abstract: A processing device in a memory system assigns a memory page to a sensitivity tier of a plurality of sensitivity tiers. The processing device determines respective scan intervals for the plurality of sensitivity tiers, wherein the respective scan intervals are based on at least one characteristic of a memory device, the at least one characteristic comprising memory cell margins of the memory device. The processing device scans a subset of a plurality of memory pages, wherein the subset comprises a number of memory pages from each sensitivity tier identified according to the respective scan intervals.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 21, 2022
    Inventors: Kishore Kumar Muchherla, Gary F. Besinga, Cory M. Steinmetz, Pushpa Seetamraju, Jiangang Wu, Sampath K. Ratnam, Peter Feeley
  • GROUPING BLOCKS BASED ON POWER CYCLE AND POWER ON TIME
    Publication number: 20220229554
    Abstract: A block family associated with a memory device is initialized. An initial value of a power cycle count associated with the memory device is stored. Responsive to programming a block residing in the memory device, the block is associated with the block family. Responsive to determining that a current value of the power cycle count exceeds the initial value of the power cycle count, the block family is closed. Responsive to determining that a time period that has elapsed since initializing the block family exceeds a threshold period, the block family is closed.
    Type: Application
    Filed: January 20, 2021
    Publication date: July 21, 2022
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Peter Feeley, Karl D. Schuh
  • Mitigating a voltage condition of a memory cell in a memory sub-system
    Patent number: 11393541
    Abstract: A determination that a programming operation has been performed on a memory cell can be made. An amount of time that has elapsed since the programming operation has been performed on the memory cell can be identified. A determination as to whether the amount of time that has elapsed satisfies a threshold time condition can be made. In response to determining that the amount of time that has elapsed satisfies the threshold time condition an operation can be performed on the memory cell to change or maintain a voltage condition of the memory cell.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy, Qisong Lin, Shane Nowell, Mustafa N. Kaynak
  • Power-on-time based data relocation
    Patent number: 11379355
    Abstract: A total estimated occupancy value of a first data on a first data block of a plurality of data blocks is determined. To determine the total estimated occupancy value of the first data block, a total block power-on-time (POT) value of the first data block is determined. Then, a scaling factor is applied to the total block POT value to determine the total estimated occupancy value of the first data block. Whether the total estimated occupancy value of the first data block satisfies a threshold criterion is determined. Responsive to determining that the total estimated occupancy value of the first data block satisfies the threshold criterion, data stored at the first data block is relocated to a second data block of the plurality of data blocks.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Renato C. Padilla, Sampath K. Ratnam, Saeed Sharifi Tehrani, Peter Feeley, Kevin R. Brandt
  • TRIM SETTING DETERMINATION FOR A MEMORY DEVICE
    Publication number: 20220180954
    Abstract: The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.
    Type: Application
    Filed: February 25, 2022
    Publication date: June 9, 2022
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • TEMPERATURE-AWARE DATA MANAGEMENT IN MEMORY SUB-SYSTEMS
    Publication number: 20220171713
    Abstract: At least one source physical memory block stored in a memory device is identified. The source physical memory block comprises at least one logical unit. A determination is made as to whether an age characteristic of the logical unit satisfies a threshold criterion. A storage classification is determined for the logical unit based on whether the age characteristic of the logical unit satisfies the threshold criterion. The classification comprises a hot data classification or a cold data classification. A target physical memory block is identified based on the storage classification determined for the logical unit, and the logical unit is stored in the identified target physical memory block.
    Type: Application
    Filed: August 11, 2021
    Publication date: June 2, 2022
    Inventors: Ashutosh Malshe, Sampath Ratnam, Kishore Kumar Muchherla, Peter Feeley
  • CACHE MANAGEMENT BASED ON MEMORY DEVICE OVER-PROVISIONING
    Publication number: 20220156187
    Abstract: System and methods are disclosed include a memory device and a processing device coupled to the memory device. The processing device can determine an amount of valid management units in a memory device of a memory sub-system. The processing device can then determine a surplus amount of valid management units on the memory device based on the amount of valid management units. The processing device can then configure a size of a cache of the memory device based on the surplus amount of valid management units.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 19, 2022
    Inventors: Kevin R. Brandt, Peter Feeley, Kishore Kumar Muchherla, Yun Li, Sampath K. Ratnam, Ashutosh Malshe, Christopher S. Hale, Daniel J. Hubbard
  • TRIM SETTING DETERMINATION ON A MEMORY DEVICE
    Publication number: 20220138100
    Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • EXTENDED CROSS-TEMPERATURE HANDLING IN A MEMORY SUB-SYSTEM
    Publication number: 20220129204
    Abstract: An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.
    Type: Application
    Filed: November 1, 2021
    Publication date: April 28, 2022
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
  • Selective accelerated sampling of failure-sensitive memory pages
    Patent number: 11301143
    Abstract: A processing device in a memory system determines sensitivity value of a memory page in the memory system. The processing device assigns the memory page to a sensitivity tier of a plurality of sensitivity tiers based on a corresponding sensitivity value, wherein each sensitivity tier has a corresponding range of sensitivity values. The processing device further determines a targeted scan interval for each sensitivity tier of the plurality of sensitivity tiers and scans a subset of a plurality of memory pages in the memory component, wherein the subset comprises a number of memory pages from each sensitivity tier determined according to the corresponding targeted scan interval of each sensitivity tier.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Gary F. Besinga, Cory M. Steinmetz, Pushpa Seetamraju, Jiangang Wu, Sampath K. Ratnam, Peter Feeley
  • BLOCK FAMILY-BASED ERROR AVOIDANCE FOR MEMORY DEVICES
    Publication number: 20220091741
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Inventors: Michael Sheperek, Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz
  • MEMORY DEVICES AND ELECTRONIC SYSTEMS HAVING A HYBRID CACHE INCLUDING STATIC AND DYNAMIC CACHES, AND RELATED METHODS
    Publication number: 20220091740
    Abstract: Memory devices are disclosed. A memory device may include dynamic cache, static cache, and a memory controller. The memory controller may be configured to disable the static cache responsive to a number of program/erase (PE) cycles consumed by the static cache being greater than an endurance of the static cache. The memory controller may also be configured to disable the dynamic cache responsive to a number of PE cycles consumed by the dynamic cache being greater than an endurance of the dynamic cache. Associated methods and systems are also disclosed.
    Type: Application
    Filed: December 3, 2021
    Publication date: March 24, 2022
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Sampath k. Ratnam, Peter Feeley, Michael G. Miller, Christopher S. Hale, Renato C. Padilla
  • ASSOCIATING MULTIPLE CURSORS WITH BLOCK FAMILY OF MEMORY DEVICE
    Publication number: 20220066639
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to perform operations comprising opening a block family associated with the memory device; initialize a timer associated with the block family; assigning a plurality of cursors to the block family; responsive to programming a first block associated with a first cursor of the memory device, associating the first block with the block family; responsive to programming a second block associated with a second cursor of the memory device, associating the second block with the block family; and responsive to detecting expiration of the timer, closing the block family.
    Type: Application
    Filed: November 5, 2020
    Publication date: March 3, 2022
    Inventors: Michael Sheperek, Bruce A. Liikanen, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz
  • Trim setting determination for a memory device
    Patent number: 11264112
    Abstract: Apparatuses and methods related to a memory system including a controller and an array of memory cells are provided. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • Cache management based on memory device over-provisioning
    Patent number: 11256620
    Abstract: System and methods are disclosed include a memory device and a processing device coupled to the memory device. The processing device can determine an amount of valid blocks in a memory device of a memory sub-system. The processing device can then determine a surplus amount of valid blocks on the memory device based on the amount of valid blocks. The processing device can then configure a size of a cache of the memory device based on the surplus amount of valid blocks.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Brandt, Peter Feeley, Kishore Kumar Muchherla, Yun Li, Sampath K. Ratnam, Ashutosh Malshe, Christopher S. Hale, Daniel J. Hubbard
  • DATA BLOCK SWITCHING AT A MEMORY SUB-SYSTEM
    Publication number: 20220050772
    Abstract: Incoming host data is programmed to a first set of data blocks indicated by a first cursor of a memory sub-system. The first set of blocks is associated with a first write mode. A determination is made that a second set of blocks associated with a second write mode is available to store the incoming host data prior to closing one or more of the first set of blocks. The incoming host data is programmed to the second set of blocks in view of a second cursor of the memory sub-system. A media management operation is performed to close the one or more of the first set of blocks.
    Type: Application
    Filed: October 27, 2021
    Publication date: February 17, 2022
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Kevin R. Brandt, Cory M. Steinmetz
  • RELOCATING DATA TO LOW LATENCY MEMORY
    Publication number: 20220027062
    Abstract: A processing device in a memory sub-system identifies a plurality of word lines at a first portion of a memory device, determines a respective error rate for each of the plurality of word lines, and determines that a first error rate of a first word line of the plurality of word lines and a second error rate of a second word line of the plurality of word lines satisfy a first threshold condition pertaining to an error rate threshold. The processing device further identifies a third word line of the plurality of word lines that is proximate to the first word line and the second word line and relocates data stored at the third word line to a second portion of the memory device, wherein the second portion of the memory device is associated with a lower read latency than the first portion of the memory device.
    Type: Application
    Filed: October 12, 2021
    Publication date: January 27, 2022
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Harish R. Singidi, Peter Feeley
  • Block family-based error avoidance for memory devices
    Patent number: 11231863
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: January 25, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Michael Sheperek, Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz
  • Trim setting determination on a memory device
    Patent number: 11226896
    Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • OPERATION OF MIXED MODE BLOCKS
    Publication number: 20220013182
    Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Gary F. Besinga, Scott A. Stoller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley