Abstract: A computer system and a method for enhancing the cache prefetch behavior. A computer system including a processor, a main memory, a prefetch controller, a cache memory, a prefetch buffer, and a main memory, wherein each page in the main memory has associated with it a tag, which is used for controling the prefetching of a variable subset of lines from this page as well as lines from at least one other page. And, coupled to the processor is a prefetch controller, wherein the prefetch controller responds to the processor determining a fault (or miss) occurred to a line of data by fetching a corresponding line of data with the corresponding tag, with the corresponding tag to be stored in the prefetch buffer, and sending the corresponding line of data to the cache memory.

Abstract: A computer system and a method for enhancing the cache prefetch behavior. A computer system including a processor, a main memory, a prefetch controller, a cache memory, a prefetch buffer, and a main memory, wherein each page in the main memory has associated with it a tag, which is used for controlling the prefetching of a variable subset of lines from this page as well as lines from at least one other page. And, coupled to the processor is a prefetch controller, wherein the prefetch controller responds to the processor determining a fault (or miss) occurred to a line of data by fetching a corresponding line of data with the corresponding tag, with the corresponding tag to be stored in the prefetch buffer, and sending the corresponding line of data to the cache memory.

Abstract: A exemplary system and method are provided for learning and cache management in software defined contexts. Exemplary embodiments of the present invention described herein address the problem of the data access wall resulting from processor stalls due to the increasing discrepancies between processor speed and the latency of access to data that is not stored in the immediate vicinity of the processor requesting the data.

Abstract: A system and method of detecting and forecasting resource bottlenecks of a computer system. In one aspect, a method includes the steps of: monitoring with successive measurements a utilization parameter of a system resource; computing a change parameter by comparing the differences between successive measurements of the utilization parameter; comparing the change parameter to a threshold change parameter; and reporting a resource bottleneck if the change parameter exceeds the threshold change parameter.

Abstract: A computer compressed memory system for storing and retrieving data in a processing system, includes a memory including at least one memory device for storing at least one of uncompressed data and compressed data, a compressor for encoding data blocks into smaller compressed data blocks for storage in the memory, a decompressor for reconstituting encoded data into original uncompressed data blocks, a memory controller for generating, receiving and responding to memory access requests from processing and input/output units and responsively controlling access to the memory from the compressor and the decompressor for storing and retrieving data, and a hardware priority filter associated with the memory controller for selecting specific memory access requests according to attributes and access type within prescribed rates and under specific conditions.

Abstract: A method and system for memory management are provided. The system includes a tag cache in communication with one or more cache devices in a storage hierarchy. The tag cache includes tags of recently accessed memory blocks, each tag corresponding to one of the memory blocks and including tag contents. The tag contents control which memory lines of the corresponding memory block are prefetched into at least one of the cache devices. The tag contents further include a bit to control prefetching of memory lines from a next virtual memory block, the bit referred to as a next virtual memory block bit. The next virtual memory block bit in a preceding memory block in a virtual address space is set to a prefetch status when the preceding memory block tag is in the tag cache.

Abstract: A method and structure is disclosed for constraining cache line replacement that processes a cache miss in a computer system. The invention contains a K-way set associative cache that selects lines in the cache for replacement. The invention constrains the selecting process so that only a predetermined subset of each set of cache lines is selected for replacement. The subset has at least a single cache line and the set size is at least two cache lines. The invention may further select between at least two cache lines based upon which of the cache lines was accessed least recently. A selective enablement of the constraining process is based on a free space memory condition of a memory associated with the cache memory. The invention may further constrain cache line replacement based upon whether the cache miss is from a non-local node in a nonuniform-memory-access system. The invention may also process cache writes so that a predetermined subset of each set is known to be in an unmodified state.

Abstract: We present a “directory extension” (hereinafter “DX”) to aid in prefetching between proximate levels in a cache hierarchy. The DX may maintain (1) a list of pages which contains recently ejected lines from a given level in the cache hierarchy, and (2) for each page in this list, the identity of a set of ejected lines, provided these lines are prefetchable from, for example, the next level of the cache hierarchy. Given a cache fault to a line within a page in this list, other lines from this page may then be prefetched without the substantial overhead to directory lookup which would otherwise be required.

Abstract: Exemplary embodiments are described herein whereby blocks of data are losslessly compressed and decompressed using a nested hierarchy of fixed phrase length dictionaries. The dictionaries may be built using information related to the manner in which data is commonly organized in computer systems for convenient retrieval, processing, and storage. This results in low cost designs that give significant compression. Further, the methods can be implemented very efficiently in hardware.

Abstract: In a computer system in which a plurality of hosts is connected through an interconnection network, an apparatus coupled to the interconnection network for allowing the plurality of hosts to share a collection of memory sectors, the memory sectors storing compressed data, is provided. The apparatus includes a network adapter for coupling the apparatus to the interconnection network; a memory for storing the collection of memory sectors; and control logic for managing the memory, the control logic including a memory compressor/decompressor. The memory further includes a directory for translating real addresses of at least one host to an address in the apparatus. A method for managing a number of memory sectors used by each host and a method for translating a real address specified by at least one host into a real address of the apparatus is also provided.

Abstract: A system and method preprocesses data, in a computer system where forecasting of computing resources is performed based on past and present observations of measurements related to the resources. The preprocessing includes decomposing the past and present observations into a smooth time sequence, a jump time sequence, a noise time sequence and a spike time sequence. The method (and system) includes detecting the spikes in a signal representing the measurements, detecting the jumps in the signal, removing spikes and jumps from the signal, and removing the noise from the signal, to obtain a smooth version of the signal.

Abstract: We separate the control functions of the I/O from the actual caching and transfer of data. This is referred herein as “disk improvements.” For caching, this enables improved utilization of bandwidth and memory. For transfers of data, bandwidth is improved while retaining security. Also in the present invention, we utilize unused portions of host systems to serve as a cache. This is referred herein as “cache enhancements.

Abstract: A system for memory management including a tag controlled buffer in communication with a memory device. The memory device includes a plurality of pages divided into a plurality of individually addressable lines. The tag controlled buffer includes a prefetch buffer including at least one of the individually addressable lines from the memory device. The tag controlled buffer also includes a tag cache in communication with the prefetch buffer. The tag cache includes a plurality of tags, where each tag is associated with one of the pages in the memory device and each tag includes a pointer to at least one of the lines in the prefetch buffer. Access to the lines in the prefetch buffer is controlled by the tag cache.

Abstract: A system for memory management including a tag cache in communication with one or more cache devices in a storage hierarchy. The tag cache includes tags of recently accessed memory blocks where each tag corresponds to one of the pages and each tag includes tag contents. The tag contents control which memory lines of the corresponding memory block are prefetched into at least one of the cache devices. The tag contents are updated using a selected subset of processor references. The subset is referred to as filtered references. The tag contents are modified probabilistically at selected time or events.

Abstract: A computer system having a main memory for storing data in a compressed format and a processor cache for storing decompressed data, a method for converting the data of said main memory from compressed to uncompressed state, comprising the steps of reducing used portions of said main memory to a target value; disabling a compressor used for compressing the uncompressed data; decompressing said compressed data of said main memory; moving said decompressed data to physical addresses equal to real addresses; and releasing the memory occupied by a compressed memory director and data structures used in the above steps.

Abstract: Disclosed is a method of managing memory to prevent an operating system from writing into user memory space, the method comprising providing a translation look-aside buffer (TLB) for storing TLB entries, each said TLB entry comprising a virtual address of a page in system memory space, a real address of said page, a flag entry for storing a value F indicating whether said page is a user page in said user memory space, providing a space recovery mode register comprising a mode entry for storing a value E indicating whether the system is in a normal mode or in a space recovery mode, said value of E set to said space recovery mode when available free user space fall below a predetermined threshold value, and for each said TLB entry, designating said page in system memory space as read-only when F=0 and E=0. An alternative embodiment is also disclosed wherein no modifications to memory structures are required.

Abstract: A system and method of detecting and forecasting resource bottlenecks of a computer system. In one aspect, a method comprises the steps of: monitoring with successive measurements a utilization parameter of a system resource; computing a change parameter by comparing the differences between successive measurements of the utilization parameter; comparing the change parameter to a threshold change parameter; and reporting a resource bottleneck if the change parameter exceeds the threshold change parameter.

Abstract: A method and structure stores and/or transmits and receives data in compressed form. Retrieval latencies are reduced by selectively transmitting a portion of the data in uncompressed form. When the apparatus is part of a computer architecture supporting main memory compression, a selected L2 cache line belonging to the unit of main memory compression is kept uncompressed. To minimize decompression latency, the uncompressed L2 cache line is stored with the compressed-memory directory. Alternatively, the uncompressed L2 cache line is stored in the compressed memory together with the rest of the memory compression unit it belongs to.

Abstract: A system and method for managing a memory storage device including a physical memory having free space for storing content maintained in compressed form and organized as pages. The system includes a control device for managing performance of input and output operations of compressed content to and from the memory storage device, with output operations including a memory pageout operations for recovering free memory storage space. The control device maintains an amount of free storage space readily available for recovery to above a threshold amount so as to enable subsequent pageout operations to be performed. A novel data construct is provided that includes locations of pages which may be immediately cleared from the physical memory for a subsequent pageout operation, the control device performing a flush operation by accessing the data construct and expediently deleting one or more pages identified in the list as available for deletion.

Abstract: A method and structure stores and/or transmits and receives data in compressed form. Retrieval latencies are reduced by selectively transmitting a portion of the data in uncompressed form. When the apparatus is part of a computer architecture supporting main memory compression, a selected L2 cache line belonging to the unit of main memory compression is kept uncompressed. To minimize decompression latency, the uncompressed L2 cache line is stored with the compressed-memory directory. Alternatively, the uncompressed L2 cache line is stored in the compressed memory together with the rest of the memory compression unit it belongs to.