Abstract: A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.

Abstract: A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.

Abstract: A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.

Abstract: An electronic circuit includes a first transistor device with a control terminal and a load path. A drive circuit includes an input terminal and an output terminal. The output terminal is coupled to the control terminal of the first transistor device. The drive circuit is operable to drive the first transistor device dependent on an input signal received at the input terminal. A polarity detector is coupled in parallel with the load path of the first transistor device. The polarity detector includes a second transistor device and a current detector. The second transistor device includes a load path connected to the load path of the first transistor device. The current detector includes a sense path in series with the load path of the second transistor device and an output connected to the input terminal of the drive circuit.

Abstract: A semiconductor device including a drift zone of a first conductivity type serving as a substrate layer having a front side and a back side. A first contact electrode is arranged at the front side of the drift zone. A control region is arranged at the front side and controls an injection of carriers of at least the first conductivity type into the drift zone. A second contact electrode is arranged at the backside of the drift zone. The drift zone is arranged to carry a carrier flow between the first and the second contact electrode. The drift zone includes a silicon carbide wafer with a net carrier concentration less than 1015 cm?3 and a carrier lifetime of at least 50 ns.

Abstract: A unipolar semiconductor component having a drift layer is produced by forming the drift layer with a continuously decreasing concentration of a charge carrier doping along the growth direction of the drift layer by way of epitaxial precipitation of the material of the drift layer, which comprises at least one wide band gap material. By using silicon carbide for the drift layer formed by the epitaxial precipitation, a subsequent change of the continuously decreasing concentration of the charge carrier doping due to a diffusion of the dopant atoms in downstream processes is suppressed. The production method can be used in particular to implement a unipolar semiconductor component comprising a drift layer, which component has an advantageous ratio of a comparatively high reverse bias voltage with relatively low forward losses, in a simple and/or cost-effective manner. The unipolar semiconductor component can be an active or passive semiconductor component.

Abstract: An electronic circuit includes a first transistor device with a control terminal and a load path. A drive circuit includes an input terminal and an output terminal. The output terminal is coupled to the control terminal of the first transistor device. The drive circuit is operable to drive the first transistor device dependent on an input signal received at the input terminal. A polarity detector is coupled in parallel with the load path of the first transistor device. The polarity detector includes a second transistor device and a current detector. The second transistor device includes a load path connected to the load path of the first transistor device. The current detector includes a sense path in series with the load path of the second transistor device and an output connected to the input terminal of the drive circuit.

Abstract: A manufacturing method provides a semiconductor device having a semiconductor body defining a source region, a body region, a drift region and a diode region. The drift region has a first drift region section and a second drift region section. The diode region is buried within the drift region, and has a semiconductor type opposite to the drift region to form a diode. The diode region is separated from the gate electrode by the first drift region section extending from the diode region in a vertical direction. The gate electrode is adjacent the body region and insulated from the body region by a gate dielectric. A source electrode is electrically connected to the source region, the body region and the diode region. A semiconductor region of a doping type opposite to the doping type of the drift region is arranged between the first drift region section and the source electrode.

Abstract: A manufacturing method provides a semiconductor device having a semiconductor body defining a source region, a body region, a drift region and a diode region. The drift region has a first drift region section and a second drift region section. The diode region is buried within the drift region, and has a semiconductor type opposite to the drift region to form a diode. The diode region is separated from the gate electrode by the first drift region section extending from the diode region in a vertical direction. The gate electrode is adjacent the body region and insulated from the body region by a gate dielectric. A source electrode is electrically connected to the source region, the body region and the diode region. A semiconductor region of a doping type opposite to the doping type of the drift region is arranged between the first drift region section and the source electrode.

Abstract: The invention relates to a production method for a unipolar semiconductor component having a drift layer (16), comprising the following step: forming the drift layer (16) with a continuously decreasing concentration of a charge carrier doping (n) along the growth direction (19) of the drift layer (16) by way of epitaxial precipitation of the material of the drift layer (16), which comprises at least one wide band gap material. By using silicon carbide for the drift layer (16) formed by the epitaxial precipitation, a subsequent change of the continuously decreasing concentration of the charge carrier doping (n) due to a diffusion of the dopant atoms in downstream processes is suppressed. The production method can be used in particular to implement a unipolar semiconductor component comprising a drift layer (16), which component has an advantageous ratio of a comparatively high reverse bias voltage with relatively low forward losses, in a simple and/or cost-effective manner.

Abstract: A semiconductor device including a drift zone of a first conductivity type serving as a substrate layer having a front side and a back side. A first contact electrode is arranged at the front side of the drift zone. A control region is arranged at the front side and controls an injection of carriers of at least the first conductivity type into the drift zone. A second contact electrode is arranged at the backside of the drift zone. The drift zone is arranged to carry a carrier flow between the first and the second contact electrode. The drift zone includes a silicon carbide wafer with a net carrier concentration less than 1015 cm?3 and a carrier lifetime of at least 50 ns.

Abstract: A transistor component having a shielding structure. One embodiment provides a source terminal, a drain terminal and control terminal. A source zone of a first conductivity type is connected to the source terminal. A drain zone of the first conductivity type is connected to the drain terminal. A drift zone is arranged between the source zone and the drain zone. A junction control structure is provided for controlling a junction zone in the drift zone between the drain zone and the source zone, at least including one control zone. A shielding structure is arranged in the drift zone between the junction control structure and the drain zone and at least includes a shielding zone of a second conductivity type being complementarily to the first conductivity type. The shielding zone is connected to a terminal for a shielding potential.

Abstract: A method for manufacturing a silicon carbide single crystal. A silicon carbide single crystal is grown. The crystal has a boron concentration less than 5×1014 cm?3, and a concentration of transition metals impurities less than 5×1014 cm?3. Intrinsic defects in the crystal are minimised. The intrinsic defects include silicon vacancies or carbon vacancies. The crystal is annealed for a desired time at a temperature above 700° C. in an atmosphere containing any of the gases hydrogen or a mixture of hydrogen and an inert gas, such that the density of intrinsic defects and any associated defects is decreased to a concentration low enough to confer to the crystal a desired carrier life time of at least 50 ns at room temperature.

Abstract: A transistor component having a shielding structure. One embodiment provides a source terminal, a drain terminal and control terminal. A source zone of a first conductivity type is connected to the source terminal. A drain zone of the first conductivity type is connected to the drain terminal. A drift zone is arranged between the source zone and the drain zone. A junction control structure is provided for controlling a junction zone in the drift zone between the drain zone and the source zone, at least including one control zone. A shielding structure is arranged in the drift zone between the junction control structure and the drain zone and at least includes a shielding zone of a second conductivity type being complementarily to the first conductivity type. The shielding zone is connected to a terminal for a shielding potential.

Abstract: An embodiment of the invention relates to a switching system that includes a depletion-mode semiconductor device, such as a silicon carbide device, coupled in series with an enhancement-mode semiconductor device, such as a silicon field effect transistor, so that a controller can be configured to disable conductivity of the series arrangement of the two switches during a transient operating condition. During normal high-frequency switching operation, the controller persistently enables the enhancement-mode device to conduct while intermittently enabling the depletion-mode device to conduct. The controller disables the enhancement-mode device to conduct during a transient operating condition such as start up or during a fault, thereby providing circuit protection during such transients. The switching system preserves low loss switching characteristics of the depletion-mode device in a high-frequency switching circuit.

Abstract: A method for making an integrated circuit including vertical junction field effect transistors is disclosed. One embodiment creates a vertical junction field effect transistor using a fault-tolerant or alignment-tolerant production process. The device performance is not harmed, even if misalignments in consecutive semiconductor processing steps occur.

Abstract: An integrated vertical SiC—PN power diode has a highly doped SiC semiconductor body of a first conductivity type, a low-doped drift zone of the first conductivity type, arranged above the semiconductor body on the emitter side, an emitter zone of a second conductivity type, applied to the drift zone, and at least one thin intermediate layer of the first conductivity type. The intermediate layer is arranged inside the drift zone, has a higher doping concentration than the drift zone, and divides the drift zone into at least one first anode-side drift zone layer and at least one second cathode-side drift zone layer. There is also disclosed a circuit configuration with such SiC—PN power diodes.

Abstract: An embodiment of the invention relates to a switching system that includes a depletion-mode semiconductor device, such as a silicon carbide device, coupled in series with an enhancement-mode semiconductor device, such as a silicon field effect transistor, so that a controller can be configured to disable conductivity of the series arrangement of the two switches during a transient operating condition. During normal high-frequency switching operation, the controller persistently enables the enhancement-mode device to conduct while intermittently enabling the depletion-mode device to conduct. The controller disables the enhancement-mode device to conduct during a transient operating condition such as start up or during a fault, thereby providing circuit protection during such transients. The switching system preserves low loss switching characteristics of the depletion-mode device in a high-frequency switching circuit.

Abstract: A method for manufacturing a silicon carbide single crystal. A silicon carbide single crystal is grown. The crystal has a boron concentration less than 5×1014 cm?3, and a concentration of transition metals impurities less than 5×1014 cm?3. Intrinsic defects in the crystal are minimised. The intrinsic defects include silicon vacancies or carbon vacancies. The crystal is annealed for a desired time at a temperature above 700° C. in an atmosphere containing any of the gases hydrogen or a mixture of hydrogen and an inert gas, such that the density of intrinsic defects and any associated defects is decreased to a concentration low enough to confer to the crystal a desired carrier life time of at least 50 ns at room temperature.

Abstract: A method for making an integrated circuit including vertical junction field effect transistors is disclosed. One embodiment creates a vertical junction field effect transistor using a fault-tolerant or alignment-tolerant production process. The device performance is not harmed, even if misalignments in consecutive semiconductor processing steps occur.